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PDF LM1851 Data sheet ( Hoja de datos )

Número de pieza LM1851
Descripción Ground Fault Interrupter
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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June 1992
LM1851 Ground Fault Interrupter
General Description
The LM1851 is designed to provide ground fault protection
for AC power outlets in consumer and industrial environ-
ments Ground fault currents greater than a presettable
threshold value will trigger an external SCR-driven circuit
breaker to interrupt the AC line and remove the fault condi-
tion In addition to detection of conventional hot wire to
ground faults the neutral fault condition is also detected
Full advantage of the U S UL943 timing specification is tak-
en to insure maximum immunity to false triggering due to
line noise Special features include circuitry that rapidly re-
sets the timing capacitor in the event that noise pulses intro-
duce unwanted charging currents and a memory circuit that
allows firing of even a sluggish breaker on either half-cycle
of the line voltage when external full-wave rectification is
used
Features
Y Internal power supply shunt regulator
Y Externally programmable fault current threshold
Y Externally programmable fault current integration time
Y Direct interface to SCR
Y Operates under line reversal both load vs line and hot
vs neutral
Y Detects neutral line faults
Block and Connection Diagram
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Order Number LM1851M or LM1851N
See NS Package Number M08A or N08E
TL H 5177 – 1
C1995 National Semiconductor Corporation TL H 5177
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RRD-B30M115 Printed in U S A

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Application Circuits
A typical ground fault interrupter circuit is shown in Figure 2
It is designed to operate on 120 VAC line voltage with 5 mA
normal fault sensitivity
start-up (S1 closure) with both a heavy normal fault and a
2X grounded neutral fault present This situation is shown dia-
gramatically below
A full-wave rectifier bridge and a 15k 2W resistor are used
to supply the DC power required by the IC A 1 mF capacitor
at pin 8 used to filter the ripple of the supply voltage and is
also connected across the SCR to allow firing of the SCR on
either half-cycle When a fault causes the SCR to trigger
the circuit breaker is energized and line voltage is removed
from the load At this time no fault current flows and the IC
discharge current increases from ITH to 3ITH (see Circuit
Description and Block Diagram) This quickly resets both
the timing capacitor and the output latch At this time the
circuit breaker can be reset and the line voltage again sup-
plied to the load assuming the fault has been removed A
1000 1 sense transformer is used to detect the normal fault
The fault current which is basically the difference current
TL H 5177 – 5
between the hot and neutral lines is stepped down by 1000
UL943 specifies s25 ms average trip time under these con-
and fed into the input pins of the operational amplifier
through a 10 mF capacitor The 0 0033 mF capacitor be-
ditions Calculation of Ct based upon charging currents due
to normal fault only is as follows
tween pin 2 and pin 3 and the 200 pF between pins 3 and 4
s25 ms Specification
are added to obtain better noise immunity The normal fault
sensitivity is determined by the timing capacitor discharging
current ITH ITH can be calculated by
7V
ITHeRSETd2
(1)
At the decision point the average fault current just equals
the threshold current ITH
ITHeIf(r2ms)c0 91
(2)
where If(rms) is the rms input fault current to the operational
amp and the factor of 2 is due to the fact that If charges the
timing capacitor only during one half-cycle while ITH dis-
b3 ms GFI turn-on time (15k and 1 mF)
b8 ms Potential loss of one half-cycle due to fault current
sense of half-cycles only
b4 ms Time required to open a sluggish circuit breaker
s10 ms Maximum integration time that could be allowed
8 ms Value of integration time that accommodates com-
ponent tolerances and other variables
IcT
Ct e V
(5)
where T e integration time
V e threshold voltage
charges the capacitor
verts the rms value to
continuously The
an average value
Cfaocmtobrin0in9g1Deqcaouanta-- Sheet4U.cIoemaverage
fault
current
into
Ct
tions (1) and (2) we have
7V
RSETeIf(rms)c0 91
 J  JI e 120 VAC(rms)
c
RN
(3)
X RB Y
XRG a RNY
For example to obtain 5 mA(rms) sensitivity for the circuit in
Figure 2 we have
7V
RSETe5 mAc0 91e1 5M X
(4)
heavy fault
current generated
(swamps ITH)
portion of
fault current
shunted
around GFI
1000
The correct value for RSET can also be determined from the
characteristic curve that plots equation (3) Note that this is
an approximate calculation the exact value of RSET de-
pends on the specific sense transformer used and LM1851
tolerances Inasmuch as UL943 specifies a sensitivity ‘‘win-
dow’’ of 4 mA–6 mA provision should be made to adjust
RSET on a per-product basis
Independent of setting sensitivity the desired integration
time can be obtained through proper selection of the timing
 J  J1 turn
1
c c c (0 91)
1000 turns
2
X Y XY X Y
current
division of
input sense
transformer
therefore
Ct charging
on half-
cycles only
rms to
average
conversion
(6)
capacitor Ct Due to the large number of variables involved
proper selection of Ct is best done empirically The following
design example then should only be used as a guideline
Assume the goal is to meet UL943 timing requirements
 J  J  J  J (Cte
120 0 4
11
c c c c(0 91)
500 1 6a0 4 1000 2
17 5
c0 0008
(7)
Also assume that worst case timing occurs during GF1
Cte 0 01 mF
5
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