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PDF TEA1771 Data sheet ( Hoja de datos )

Número de pieza TEA1771
Descripción GreenChip PC primary control IC
Fabricantes NXP Semiconductors 
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No Preview Available ! TEA1771 Hoja de datos, Descripción, Manual

TEA1771
GreenChip PC primary control IC
Rev. 01 — 6 February 2009
Product data sheet
www.datasheet4u.com
1. General description
The TEA1771 is a primary control IC for an active clamp forward converter. This converter
enables higher duty cycles of up to 70 %. A higher maximum duty cycle lowers the
required breakdown voltage of both the primary and secondary switches, reducing the
total cost of the system.
The IC is optimized for (ATX) PC power supplies. Together with the TEA1781 and
TEA1782 a unique system can be made that reduces costs by integrating the standby
supply. It assures high output voltage accuracy and avoids cross regulation as the output
voltages are regulated separately. This system exceeds the current and proposed
efficiency standards such as 80 plus-gold, energy star and blue angel.
The TEA1771 is implemented in the high voltage EZ-HV SOI process. It enables direct
start-up from the rectified mains voltage, excluding the need for a start-up resistor. The
high voltage reset switch, required for the active clamp, is integrated in the IC. The IC has
a feed-forward control regulation, avoiding high resonant voltage peaks as a result of
output load or input voltage transients. This also assures proper regulation of the output
voltages at input voltage variations.
2. Features
I Designed for ATX PC power supplies
I Universal mains operation, 90 V (AC) to 265 V (AC)
I Integrated start-up current source
I Integrated high-voltage, high-side active clamp reset switch
I Feed-forward regulation
I Enhanced efficiency in Standby mode and Normal mode
I OverVoltage Protection (OVP)
I OverCurrent Protection (OCP)
I Short-Winding Protection (SWP)
I Low external component count
I Soft (re)start
I High voltage ramp-up detection assuring Zero Voltage Switching (ZVS) of the reset
switch
I Available in a 24-pin SO package
3. Applications
I PC desktop power supply

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TEA1771 pdf
NXP Semiconductors
TEA1771
GreenChip PC primary control IC
www.datasheet4u.com
Table 3.
Symbol
n.c
CB
DM1
Pin description …continued
Pin Description
22 not connected
23 boost capacitor
24 drain main switch (M1)
8. Functional description
8.1 Introduction
The TEA1771 is designed to cooperate with the TEA1781 and the TEA1782 secondary
side controllers in a forward converter topology, see Figure 11. A typical application area
of this converter is a power supply for a desktop PC.
The topology supported by the TEA1771 enables transformer resetting using an active
reset mechanism. For this purpose a reset switch in the form of a lateral IGBT has been
integrated into the IC. This reset switch can operate high-side using an external boost
capacitor.
Advantage of this active reset mechanism is, compared to a third winding solution, that a
higher maximum duty cycle (> 50%) can be achieved. Reducing dissipation by recovering
energy is another advantage of the reset mechanism when compared to the standard
R/C/D topology.
The TEA1771 has a feed-forward control regulation, avoiding high resonant voltage peaks
as a result of output load or input voltage transients.
8.2 Supply
At power-up, the primary and secondary ICs are not yet supplied via the auxiliary
windings as the main switch M1 is off, see Figure 11. Initially, before start-up, the primary
IC is in Charge mode and supplies itself with a current Ich(LVIN) from the high voltage pin
DM2, see the SUPPLY block in Figure 1. The voltage on pin DM2 is equal to the input
voltage in this static situation. It is connected to the input via the transformer and the
parallel diode of the reset switch, Drst, see Figure 11. In Charge mode LVIN is charged
from DM2 via an internal current source, Ich(LVIN). From LVIN the nodes DECVCC and
DECPVCC are supplied by internal regulators. As a result, when LVIN is charged, the
DECVCC and DECPVCC nodes, which are decoupled by external capacitors, are
charged simultaneously. This is illustrated in the left part of Figure 3.
When the voltage at LVIN reaches its start level Vstartup(LVIN) and the voltage on pin VRST
is in its start-up window, the IC enters Running mode and starts switching; see M1 signal
in Figure 3. The voltage on pin VRST is in the start-up window when the voltage on pin
VRST is between the minimum start voltage, Vstart(VRST)(min), and the maximum start
voltage, Vstart(VRST)(max). These start-up conditions are pointed out in the
STATE DIAGRAM block in Figure 1. If the logic signal VVRSTOK is high, the voltage VVRST
is in the start-up window.
TEA1771_1
Product data sheet
Rev. 01 — 6 February 2009
© NXP B.V. 2009. All rights reserved.
5 of 25

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TEA1771 arduino
NXP Semiconductors
TEA1771
GreenChip PC primary control IC
www.datasheet4u.com
When the PSU is in Normal mode the duty cycle is independent of the operating
frequency. The frequency is set to the maximum level and is proportional to IIREF. See
Section 8.4.
f osc(max)
=
-I--I--R---E---F-
2
(6)
fosc(max) (kHz)
IIREF (µA)
Figure 6 shows the sawtooth circuit. It also shows that the charge current of the Csaw
capacitor is proportional to IIREF. Thus both the oscillation period, tosc, and the on-time, ton,
are inverse proportional to IIREF. As a result the duty cycle, δ, is constant for varying
operating frequencies.
8.6 Non-overlap times
In the previous section the non overlap times t1 and t2 are introduced. In Figure 7 these
times are illustrated. The delays, t1 and t2 avoid overlap in the on-time of the main
switch and the reset switch. The delay t1 is listed in the characteristics table:
t1 = tno(rstsw-mainsw). The value slightly differs for Standby mode and Normal mode. In the
characteristics table this is reflected by different delay values for a high and a low IOPTO
value that hold in Normal mode and Standby mode, respectively.
The delay t2 is less straightforward. It depends on the VDM1 signal. Figure 7 illustrates
the mechanism showing stylized signals. When M1 is turned off the DM1 node is charged
by the magnetizing current until it is clamped to the reset voltage. The primary controller
waits for DM1 to be charged to the reset voltage before M2 is turned on. In fact, when this
ramp has finished the controller waits an additional time, twait after which M2 is turned on.
The DM1 voltage signal varies strongly as the PSU load is varied. By sensing the VDM1
ramp-up, hard switching of the reset switch is avoided in all load conditions.
tno(bu)
M1
Vrst
TEA1771_1
Product data sheet
VDM1
M2
tramp
twait
014aaa727
Fig 7. t2 non-overlap time between the main switch (mainsw) being turned off and the
reset switch (rstw) being turned on.
If (dV/dt)r is below detection level the VDM1 ramp-up is not sensed at all. In that case a
delay is applied which, like t1, is determined by the IC itself. This delay is called tno(bu),
the backup delay. In Figure 7 this delay is illustrated by the dashed variant of M2. Counting
time from the moment M1 is turned off M2 is turned after a delay of tno(bu) has passed.
Rev. 01 — 6 February 2009
© NXP B.V. 2009. All rights reserved.
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