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PDF USBLC6-4 Data sheet ( Hoja de datos )

Número de pieza USBLC6-4
Descripción Very low capacitance ESD protection
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! USBLC6-4 Hoja de datos, Descripción, Manual

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USBLC6-4
Very low capacitance ESD protection
Features
4 data lines protection
Protects VBUS
Very low capacitance: 3 pF typ.
SOT23-6L package
RoHS compliant
Benefits
Very low capacitance between lines to GND for
optimized data integrity and speed
Low PCB space consumption, 9 mm²
maximum foot print
Enhanced ESD protection. IEC 61000-4-2 level
4 compliance guaranteed at device level,
hence greater immunity at system level
ESD protection of VBUS. Allows ESD current
flowing to Ground when ESD event occurs on
data line
High reliability offered by monolithic integration
Low leakage current for longer operation of
battery powered devices
Fast response time
Consistent D+ / D- signal balance:
– Best capacitance matching tolerance
I/O to GND = 0.015 pF
– Compliant with USB 2.0 requirements
< 1 pF
Complies with the following standards
IEC 61000-4-2 level 4:
– 15 kV (air discharge)
– 8 kV (contact discharge)
SOT23-6L
Applications
USB 2.0 ports up to 480 Mb/s (high speed)
Backwards compatible with USB 1.1 low and
full speed
Ethernet port: 10/100 Mb/s
SIM card protection
Video line protection
Portable electronics
Description
The USBLC6-4SC6 is a monolithic application
specific device dedicated to ESD protection of
high speed interfaces, such as USB 2.0, Ethernet
links and video lines.
Its very low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringent characterized ESD strikes.
Figure 1. Functional diagram
I/O1 1
GND 2
I/O2 3
6 I/O4
5 VBUS
4 I/O3
February 2008
Rev 3
1/13
www.st.com
13

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USBLC6-4 pdf
USBLC6-4
Technical information
www.datasheet4u.com
Figure 6.
ESD behavior: parasitic phenomena due to unsuitable layout
ESD sur ge on data line
VBUS
Data line
VCL+
LI/O
LI/O
di
dt
LVBUS
VCC pin
LI/O
di
dt
+ LGND
di
dt
Positive
Sur ge
I/O pin
VF
VTRANSIL
VCL
LGND
GND pin
LGND
di
dt
VTRANSIL + VF
tr = 1 ns
tr = 1 ns
- VF
t
t
VCL+
= VTRANSIL
+ VF
+
LI/O
di
dt
+
LGND
di
dt
VCL- = -VF - LI/O
di
dt
-
LGND
di
dt
V TRANSIL = VBR + Rd.Ip
sur ge > 0
sur ge > 0
-L
I/O
di
dt
- LGND
di
dt
Negative
Sur ge
VCL-
2.3 How to ensure good ESD protection
While the USBLC6-4SC6 provides high immunity to ESD surge, efficient protection depends
on the layout of the board. In the same way, with the rail to rail topology, the track from data
lines to I/O pins, from VCC to the VBUS pin and from GND plane to GND pin must be as short
as possible to avoid overvoltages due to parasitic phenomena (see Figure 7 and Figure 8 for
layout considerations)
Figure 7.
ESD behavior: optimized layout and Figure 8.
addition of a capacitance of 100 nF
ESD behavior: measurement
conditions (with coupling
capacitance)
Unsuitable layout
Optimized layout
ESD SURGE
TEST BOARD
IN OUT
USBLC6-4SC6
Vbus
5/13

5 Page





USBLC6-4 arduino
USBLC6-4
4 Package information
Package information
www.datasheet4u.com
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at www.st.com.
Table 3. SOT23-6L dimensions
E
e
b
e
A
A2
c
θ
A1
L
H
Dimensions
REF.
Millimeters
Inches
Min. Typ. Max. Min. Typ. Max.
A 0.90
1.45 0.035
0.057
A1 0
0.10 0
0.004
D A2 0.90
1.30 0.035
0.051
b 0.35
0.50 0.014
0.02
C 0.09
0.20 0.004
0.008
D 2.80
3.05 0.110
0.120
E 1.50
1.75 0.059
0.069
e 0.95
0.037
H 2.60
3.00 0.102
0.118
L 0.10
0.60 0.004
0.024
θ
10° 0°
10°
Figure 20. SOT23-6L footprint (mm)
Figure 21. SOT23-6L marking
0.60
3.50 2.30
0.95
1.20
1.10
e3
xxx
z y ww
e3: ECOPACK (Leadfree)
XXX: Marking
Z: Manufacturing location
Y: Year
WW: week
11/13

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