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PDF USBLC6-2 Data sheet ( Hoja de datos )
| Número de pieza | USBLC6-2 | |
| Descripción | VERY LOW CAPACITANCE ESD PROTECTION | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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USBLC6-2
Very low capacitance ESD protection
Features
■ 2 data lines protection
■ Protects VBUS
■ Very low capacitance: 3.5 pF max.
■ Very low leakage current: 150 nA max.
■ SOT-666 and SOT23-6L packages
■ RoHS compliant
Benefits
■ Very low capacitance between lines to GND for
optimized data integrity and speed
■ Low PCB space consumption: 2.9 mm2 max for
SOT-666 and 9mm² max for SOT23-6L
■ Enhanced ESD protection. IEC 61000-4-2 level
4 compliance guaranteed at device level,
hence greater immunity at system level
■ ESD protection of VBUS
■ High reliability offered by monolithic integration
■ Low leakage current for longer operation of
battery powered devices
■ Fast response time
■ Consistent D+ / D- signal balance:
– Very low capacitance matching tolerance
I/O to GND = 0.015 pF
– Compliant with USB 2.0 requirements
Complies with the following standards
■ IEC 61000-4-2 level 4:
– 15 kV (air discharge)
– 8 kV (contact discharge)
SOT23-6L
USBLC6-2SC6
SOT-666
USBLC6-2P6
Applications
■ USB 2.0 ports up to 480 Mb/s (high speed)
■ Compatible with USB 1.1 low and full speed
■ Ethernet port: 10/100 Mb/s
■ SIM card protection
■ Video line protection
■ Portable electronics
Description
The USBLC6-2SC6 and USBLC6-2P6 are
monolithic application specific devices dedicated
to ESD protection of high speed interfaces, such
as USB 2.0, Ethernet links and video lines.
The very low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringent characterized ESD strikes.
Figure 1. Functional diagram
I/O1 1
GND 2
I/O2 3
6 I/O1
5 VBUS
4 I/O2
March 2008
Rev 3
1/14
www.st.com
14
1 page  
USBLC6-2
Technical information
We can significantly reduce this phenomena with simple layout optimization. It is for this
reason that some recommendations have to be followed (see 2.3: How to ensure good ESD
protection).
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Figure 6.
ESD behavior: parasitic phenomena due to unsuitable layout
ESD surge on data line
VBUS
Data line
VCL+
LI/O
LI/O
di
dt
LVBUS
VCC pin
LI/O
di
dt
+
LGND
di
dt
Positive
Surge
I/O pin
VF
VTRANSIL
VCL
LGND
GND pin
LGND
di
dt
VTRANSIL + VF
tr = 1 ns
tr = 1 ns
- VF
t
t
VCL+
=
VTRANSIL
+
VF
+
LI/O
di
dt
+
LGND
di
dt
VCL- = -VF - LI/O
di
dt
-
LGND
di
dt
V TRANSIL = VBR + Rd.Ip
surge > 0
surge > 0
-LI/Oddti - LGND
di
dt
Negative
Surge
VCL-
2.3 How to ensure good ESD protection
While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on
the layout of the board. In the same way, with the rail to rail topology, the track from data
lines to I/O pins, from VCC to VBUS pin and from GND plane to GND pin must be as short as
possible to avoid overvoltages due to parasitic phenomena (see Figure 6. and Figure 7. for
layout consideration)
Figure 7. ESD behavior: layout optimization Figure 8. ESD behavior: measurement
conditions
16
25
34
Unsuitable layout
16
25
34
Optimized layout
ESD SURGE
TEST BOARD
IN OUT
+5 V
5/14
5 Page 
USBLC6-2
4 Package information
Package information
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● Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at www.st.com.
Table 3. SOT-666 dimensions
b1
L1
L3
b
D
A
E1
L2
E A3
e
Dimensions
Ref. Millimeters
Inches
Min. Typ. Max. Min. Typ. Max.
A 0.45
0.60 0.018
0.024
A3 0.08
0.18 0.003
0.007
b 0.17
0.34 0.007
0.013
b1 0.19 0.27 0.34 0.007 0.011 0.013
D 1.50
1.70 0.059
0.067
E 1.50
1.70 0.059
0.067
E1 1.10
1.30 0.043
0.051
e 0.50
0.020
L1 0.19
0.007
L2 0.10
0.30 0.004
0.012
L3 0.10
0.004
Figure 20. SOT-666 footprint
Figure 21. SOT-666 marking
0.50
0.99
0.62 2.60
e3
xxx
z y ww
e3: ECOPACK (Leadfree)
XXX: Marking
Z: Manufacturing location
Y: Year
WW: week
0.30
11/14
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet USBLC6-2.PDF ] | |
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