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PDF VS1053B Data sheet ( Hoja de datos )
| Número de pieza | VS1053B | |
| Descripción | Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC | |
| Fabricantes | VLSI | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de VS1053B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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VS1053b Datasheet
VS1053b -
Ogg Vorbis/MP3/AAC/WMA/FLAC/
MIDI AUDIO CODEC CIRCUIT
Features
Description
• Decodes
VS1053b is an Ogg Vorbis/MP3/AAC/WMA/
Ogg Vorbis;
FLAC/WAVMIDI audio decoder as well as an
MP3 = MPEG 1 & 2 audio layer III (CBR PCM/IMA ADPCM/Ogg Vorbis encoder on a
+VBR +ABR);
single chip. It contains a high-performance,
MP1/MP2 = layers I & II optional;
proprietary low-power DSP processor core
MPEG4 / 2 AAC-LC(+PNS),
VS_DSP4, data memory, 16 KiB instruction
HE-AAC v2 (Level 3) (SBR + PS);
RAM and 0.5+ KiB data RAM for user appli-
WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps); cations running simultaneously with any built-
General MIDI 1 / SP-MIDI format 0 files; in decoder, serial control and input data in-
FLAC with software plugin;
terfaces, upto 8 general purpose I/O pins, an
WAV (PCM + IMA ADPCM)
UART, as well as a high-quality variable-sample-
• Encodes Ogg Vorbis w/ software plugin rate stereo ADC (mic, line, line + mic or 2×line)
• Encodes stereo IMA ADPCM / PCM
and stereo DAC, followed by an earphone am-
• Streaming support for MP3 and WAV
plifier and a common voltage buffer.
• EarSpeaker Spatial Processing
• Bass and treble controls
VS1053b receives its input bitstream through
a serial input bus, which it listens to as a
• Operates with a single 12..13 MHz clock system slave. The input stream is decoded
• Can also be used with a 24..26 MHz clock and passed through a digital volume control
• Internal PLL clock multiplier
to an 18-bit oversampling, multi-bit, sigma-
• Low-power operation
• High-quality on-chip stereo DAC with no
phase error between channels
• Zero-cross detection for smooth volume
change
delta DAC. The decoding is controlled via a
serial control bus. In addition to the basic de-
coding, it is possible to add application spe-
cific features, like DSP effects, to the user
RAM memory.
• Stereo earphone driver capable of driv-
ing a 30 Ω load
• Quiet power-on and power-off
• I2S output interface for external DAC
Optional factory-programmable unique chip
ID provides basis for digital rights manage-
ment or unit identification features.
• Separate voltages for analog, digital, I/O
• On-chip RAM for user code and data
• Serial control and data interfaces
• Can be used as a slave co-processor
• SPI flash boot for special applications
• UART for debugging purposes
• New functions may be added with soft-
ware and upto 8 GPIO pins
• Lead-free RoHS-compliant package
Version: 1.22, 2014-12-19
1
1 page  
VS1053b Datasheet
LIST OF FIGURES
List of Figures
1 Pin configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 VS1053b in LQFP-48 packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Typical connection diagram using LQFP-48. . . . . . . . . . . . . . . . . . . . . . 13
4 SDI in VS10xx Native Mode, single-byte transfer . . . . . . . . . . . . . . . . . . 17
5 SDI in VS10xx Native Mode, multi-byte transfer, X ≥ 1 . . . . . . . . . . . . . . . 17
6 SDI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 SDI in VS1001 Mode - one byte transfer. Do not use in new designs! . . . . . . . 19
8 SDI in VS1001 Mode - two byte transfer. Do not use in new designs! . . . . . . . 19
9 SCI word read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10 SCI word write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11 SCI multiple word write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
13 Two SCI operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
14 Two SDI bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15 Two SDI bytes separated by an SCI operation . . . . . . . . . . . . . . . . . . . . 24
16 Data flow of VS1053b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17 EarSpeaker externalized sound sources vs. normal inside-the-head sound . . . 35
18 VS1053b ADC and DAC data paths with some data registers . . . . . . . . . . . 70
19 VS1053b ADC and DAC data paths with some data registers . . . . . . . . . . . 71
20 RS232 serial interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
21 I2S interface, 192 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Version: 1.22, 2014-12-19
5
5 Page 
VS1053b Datasheet
5 PACKAGES AND PIN DESCRIPTIONS
Pad Name
MICP / LINE1
MICN
XRESET
DGND0
CVDD0
IOVDD0
CVDD1
DREQ
GPIO2 / DCLK1
GPIO3 / SDATA1
GPIO6 / I2S_SCLK3
GPIO7
I2S_SDATA3
/
XDCS / BSYNC1
IOVDD1
VCO
DGND1
XTALO
XTALI
IOVDD2
DGND2
DGND3
DGND4
XCS
CVDD2
GPIO5 / I2S_MCLK3
RX
TX
SCLK
SI
SO
CVDD3
XTEST
GPIO0
LQFP
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Pin
Type
AI
AI
DI
DGND
CPWR
IOPWR
CPWR
DO
DIO
DIO
DIO
DIO
13 DI
14 IOPWR
15 DO
16 DGND
17 AO
18 AI
19 IOPWR
20 DGND
21 DGND
22 DGND
23 DI
24 CPWR
25 DIO
26 DI
27 DO
28 DI
29 DI
30 DO3
31 CPWR
32 DI
33 DIO
GPIO1
GND
GPIO4
I2S_LROUT3
AGND0
AVDD0
RIGHT
AGND1
AGND2
GBUF
34
35
/ 36
37
38
39
40
41
42
DIO
DGND
DIO
APWR
APWR
AO
APWR
APWR
AO
AVDD1
RCAP
AVDD2
LEFT
AGND3
LINE2
43 APWR
44 AIO
45 APWR
46 AO
47 APWR
48 AI
Function
Positive differential mic input, self-biasing / Line-in 1
Negative differential mic input, self-biasing
Active low asynchronous reset, schmitt-trigger input
Core & I/O ground
Core power supply
I/O power supply
Core power supply
Data request, input bus
General purpose IO 2 / serial input data bus clock
General purpose IO 3 / serial data input
General purpose IO 6 / I2S_SCLK
General purpose IO 7 / I2S_SDATA
Data chip select / byte sync
I/O power supply
For testing only (Clock VCO output)
Core & I/O ground
Crystal output
Crystal input
I/O power supply
Core & I/O ground
Core & I/O ground
Core & I/O ground
Chip select input (active low)
Core power supply
General purpose IO 5 / I2S_MCLK
UART receive, connect to IOVDD if not used
UART transmit
Clock for serial bus
Serial input
Serial output
Core power supply
Reserved for test, connect to IOVDD
Gen. purp. IO 0 (SPIBOOT), use 100 kΩ pull-down
resistor2
General purpose IO 1
I/O Ground
General purpose IO 4 / I2S_LROUT
Analog ground, low-noise reference
Analog power supply
Right channel output
Analog ground
Analog ground
Common buffer for headphones, do NOT connect to
ground!
Analog power supply
Filtering capacitance for reference
Analog power supply
Left channel output
Analog ground
Line-in 2 (right channel)
Version: 1.22, 2014-12-19
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet VS1053B.PDF ] | |
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