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PDF 92CD54IF Data sheet ( Hoja de datos )

Número de pieza 92CD54IF
Descripción TMP92CD54IF
Fabricantes Toshiba Semiconductor 
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No Preview Available ! 92CD54IF Hoja de datos, Descripción, Manual

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CMOS 32-bit Micro-controller
TMP92CD54IF
TMP92CD54I
1. Outline and Device Characteristics
TMP92CD54I is high-speed advanced 32-bit micro-controller developed for controlling
equipment which processes mass data.
TMP92CD54I is a micro-controller which has a high-performance CPU (900/H1 CPU) and
various built-in I/Os. TMP92CD54I is housed in a 100-pin mini flat package.
Device characteristics are as follows:
(1) CPU : 32-bit CPU(900/H1 CPU)
Compatible with TLCS-900,900/L,900/L1,900/H,900/H2’s instruction code
16Mbytes of linear address space
General-purpose register and register banks
Micro DMA : 8channels (250ns / 4bytes at fc = 20MHz, best case)
Minimum instruction execution time : 50ns(at 20MHz)
Internal data bus : 32-bit
(2) Internal memory
Internal RAM : 32K-byte
Internal ROM : 512K-byte Mask ROM
92CD54I-1
2006-01-27

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92CD54IF pdf
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2. Pin Assignment and Functions
2.1 Pin Assignment
TMP92CD54I
ADVSS
ADVCC
VREFL
VREFH
RX/PF7
TX/PF6
CTS1/SCLK1/PF5
RXD1/PF4
TXD1/PF3
CTS0/SCLK0/PF2
RXD0/PF1
TXD0/PF0
DVSS
PM4/SCK2
DVCC5
A8/SS/PM0
A9/MOSI/PM1
A10/MISO/PM2
A11/SECLK/PM3
D0/P00
D1/P01
D2/P02
D3/P03
D4/P04
D5/P05
01
05
10
15
20
25
TMP92CD54IF
(P-LQFP100-1414-0.50F)
14 x 14 x 1.4
TOP VIEW
75 DVCC5
X1
DVSS
X2
TEST1
70 XT1
XT2
DVCC3
PN6/SO2/SDA2/A15
PN5/SI1/SCL1/A14
65 PN4/SO1/SDA1/A13
PN3/SCK1/A12
DVSS
PN2/SI0/SCL0
DVCC5
60 PN1/SO0/SDA0
PN0/SCK0
PC0/TI0/INT1
PC1/TO1
PC2/TO3/INT2
55 PC3/TI4/INT3
PC4/TO5
PC5/TO7/INT4
REGEN
51 DVSS
Figure 2.1 TMP92CD54I Pin Assignment
92CD54I-5
2006-01-27

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92CD54IF arduino
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3.2 Memory Map
Figure 3.2 is a memory map of TMP92CD54I.
000000H
000100H
000400H
008400H
Internal I/O
(1 KByte)
Internal RAM
(32 KByte)
Direct area (n)
64Kbyte area
(nn)
010000H
External memory
TMP92CD54I
Emulator Control Area
(64K Byte)
F80000H
512 KByte
Internal ROM
(Note1)
16Mbyte area
(R)
(R)
(R+)
(R + R8/16)
(R + d8/16)
(nnn)
FFFF00H
FFFFFFH
Vector table (256 Byte)
(Note2)
( = Internal area)
Figure 3.2 Memory Map
Note1: The emulator control area is for emulator, it is mapped F00000H to F10000H address after reset.
Note2: Don’t use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved.
Note3: On emulator WR signal and RD signal are asserted, when emulator control area is accessed. Be careful to
use external memory.
Note4: Since there is a possibility of abnormal writing/reading of the data if Bus width put the different memories in
consecutive address, do not execute an access which is placed on both memories with one command.
92CD54I-11
2006-01-27

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