PDF WED3EG7233S-JD3 Data sheet ( Hoja de datos )

Número de pieza	WED3EG7233S-JD3
Descripción	256MB - 2x16Mx72 DDR SDRAM UNBUFFERED
Fabricantes	White Electronic Designs
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No Preview Available ! Whitewww.datasheet4u.com Electronic Designs WED3EG7233S-D3 -JD3 ADVANCED* 256MB – 2x16Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture DDR200 and DDR266 • JEDEC design speciﬁed Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V ± 0.20V JEDEC standard 184 pin DIMM package • JD3 PCB height: 30.48mm (1.20") DESCRIPTION The WED3EG7233S is a 2x16Mx72 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of eighteen 16Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualiﬁed or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option Clock Speed CL-tRCD-tRP OPERATING FREQUENCIES DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. May, 2005 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page Whitewww.datasheet4u.com Electronic Designs WED3EG7233S-D3 -JD3 ADVANCED IDD SPECIFICATIONS AND TEST CONDITIONS Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Symbol Conditions Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. Operating Current IDD1 One device bank; Active-Read- Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. Precharge Power- Down Standby Current IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE=(low) Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. Auto Refresh Current IDD5 tRC = tRC (MIN) Self Refresh Current IDD6 CKE ≤ 0.2V Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. DDR266@CL=2.0 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD DDR266@CL=2.5 Max 1845 2205 72 810 450 900 2250 2115 3015 72 4050 DDR200@CL=2 Max 1845 2205 72 810 450 900 2250 2115 3015 72 4050 Units mA mA rnA mA mA mA mA rnA mA mA mA White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. May, 2005 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page Whitewww.datasheet4u.com Electronic Designs WED3EG7233S-D3 -JD3 ADVANCED Document Title 256MB – 2x16Mx72 DDR SDRAM UNBUFFERED Revision History Rev # Rev A Rev 0 History Created Datasheet 0.1 Updated all specs (IDD, CAP, AC's) 0.2 Added JEDEC standard PCB (JD3) option 0.3 D3 PCB option is "NOT RECOMMENDED FOR NEW DESIGNS" 0.4 Moved from Advanced to Preliminary Release Date Status 5-22-02 Advanced 5-05 Preliminary White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. May, 2005 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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