PDF WED3EG7232S-JD3 Data sheet ( Hoja de datos )

Número de pieza	WED3EG7232S-JD3
Descripción	256MB - 32Mx72 DDR SDRAM UNBUFFERED
Fabricantes	White Electronic Designs
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No Preview Available ! www.datasheet4u.com WED3EG7232S-JD3 PRELIMINARY 256MB – 32Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture DDR200, DDR266, DDR333 amd DDR400 • JEDEC design speciﬁcations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2, 2.5 (clock) Programmable Burst Length (2, 4, 8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Power supply: • VCC = VCCQ = +2.5V ± 0.2V (100, 133 and 166MHz) • VCC = VCCQ = +2.6V ± 0.1V (200MHz) JEDEC 184 pin DIMM package • JD3 PCB height: 30.48 (1.20") Max DESCRIPTION The WED3EG7232S is a 32Mx72 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of nine 32Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualiﬁed or characterized and is subject to change without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option Clock Speed CL-tRCD-tRP DDR400 @CL=3 200MHz 3-3-3 OPERATING FREQUENCIES DDR333 @CL=2.5 DDR266 @CL=2 166MHz 133MHz 2.5-3-3 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 June 2006 Rev. 6 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page www.datasheet4u.com WED3EG7232S-JD3 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Symbol Conditions Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. Operating Current IDD1 One device bank; Active-Read- Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. Precharge Power- IDD2P All device banks idle; Power-down Down Standby Current mode; tCK=tCK (MIN); CKE=(low) Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current IDD3P One device bank active; Power- Down mode; tCK (MIN); CKE=(low) Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. Auto Refresh Current IDD5 tRC = tRC (MIN) Self Refresh Current IDD6 CKE ≤ 0.2V Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. DDR400@ CL=3 Max 1215 1530 36 540 360 630 1800 1755 2340 36 4230 DDR333@ CL=2.5 Max 1125 1530 36 450 270 540 1575 1575 2295 36 3690 DDR266@ CL=2 Max 1125 1530 36 450 270 540 1575 1575 2295 36 3690 DDR266@ CL=2.5 Max 1125 1530 36 450 270 540 1575 1575 2295 36 3690 DDR200@ CL=2 Max Units 1125 mA 1530 mA 36 rnA 450 mA 270 mA 540 mA 1575 mA 1575 rnA 2295 mA 36 mA 3690 mA June 2006 Rev. 6 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page www.datasheet4u.com WED3EG7232S-JD3 PRELIMINARY PART NUMBERING GUIDE WEDC MEMORY DDR GOLD DEPTH BUS WIDTH 2.5V SPEED (Mb/s) PACKAGE 184 PIN INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (M = Micron) (S = Samsung) (G = Inﬁneon) G = ROHS COMPLIANT WED 3 E G 72M 32 S xxx JD3 x x G June 2006 Rev. 6 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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