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Número de pieza | WED3EG6418S-D4 | |
Descripción | 128MB- 16Mx64 DDR SDRAM UNBUFFERED | |
Fabricantes | White Electronic Designs | |
Logotipo | ||
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WED3EG6418S-D4
FINAL
128MB- 16Mx64 DDR SDRAM UNBUFFERED W/PLL
FEATURES
DESCRIPTION
Double-data-rate architecture
Speed of 100MHz, 133MHz and 166MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
JEDEC standard 200 pin SO-DIMM package
Power Supply: 2.5V ± 0.25V
The WED3DG6418S is a 16Mx64 Double Data Rate
SDRAM memory module based on 128Mb DDR
SDRAM component. The module consists of eight
16Mx8 DDR SDRAMs in 66 pin TSOP package
mounted on a 200 Pin FR4 substrate.
Synchronous design allows precise cycle control
with the use of system clock. Data I/O transactions
are possible on both edges and Burst Lenths allow
the same device to be useful for a variety of high
bandwidth, high performance memory system
applications.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Oct. 2002
Rev. # 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page www.datasheet4u.com
WED3EG6418S-D4
FINAL
IDD SPECIFICATIONS AND TEST CONDITIONS
(Recommended operating conditions, tA = 0 to 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V)
Parameter
Symbol Conditions
DDR333@CL=2.5
Max
Operating Current
One device bank; Active = Precharge;
tRC=tRC(MIN); tCK=tCK
IDD0 (MIN); DQ, DM and DQS inputs changing
once per clock cycle; Address and control
inputs changing once every two cycles.
840
Operating Current
One device banks; Active-Read-Precharge;
IDD1
Burst = 2; tRC=tRC(MIN); tCK=tCK
(MIN); lOUT=0mA; Address and control inputs
changing once per clock cycle.
1040
Precharge Power-
Down Standby Current
IDD2P
All device bank idle; Power-down mode;
tCK=tCK(MIN); CKE=(low)
24
Idle Standby Current
Active Power-Down
Standby Current
CS# = High; All device banks idle;
IDD2F
tCK=tCK(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
VIN = VREF for DQ, DQS and DM.
IDD3P
One device bank active; Power-down mode;
tCK(MIN); CKE=(low)
200
280
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS(MAX);
Active Standby Current
IDD3N
tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle
495
Operating Current
Burst = 2; Reads; Continous burst; Once
IDD4R
device bank active; Address and control
inputs changing once per clock cycle;
tCK=tCK(MIN); IOUT=0mA
1280
Operating Current
Burst=2; Writes; Continous burst; Once
device bank active; Address and control
IDD4W inputs changing once per clock cycle;
tCK=tCK(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
1216
Auto Refresh Current
Self Refresh Current
IDD5 tRC=tRC(MIN)
IDD6 CKE £ 0.2V
1520
16
Operating Current
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC(MIN);
IDD7A tCK=tCK(MIN); Address and control input
change only during Active Read or Write
commands.
2640
* Module IDD was calculated on the basis of component IDD and can be different measured according to DQ loading cap.
DDR266@CL=2, 2.5
Max
760
960
24
180
280
440
1140
1040
1440
16
2400
DDR200@CL=2
Max
680
880
24
160
225
360
960
815
1315
16
1920
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Oct. 2002
Rev. # 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet WED3EG6418S-D4.PDF ] |
Número de pieza | Descripción | Fabricantes |
WED3EG6418S-D4 | 128MB- 16Mx64 DDR SDRAM UNBUFFERED | White Electronic Designs |
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