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PDF WED3DG644V-D1 Data sheet ( Hoja de datos )
| Número de pieza | WED3DG644V-D1 | |
| Descripción | 32MB - 4Mx64 SDRAM | |
| Fabricantes | White Electronic Designs | |
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White Electronic Designs
WED3DG644V-D1
32MB – 4Mx64 SDRAM, UNBUFFERED
FEATURES
PC100 and PC133 compatible
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
3.3V ± 0.3V Power Supply
144 Pin SO-DIMM JEDEC
• D1: 27.94 (1.10”)
DESCRIPTION
The WED3DG644V is a 4Mx64 synchronous DRAM
module which consists of four 4Mx16 SDRAM components
in TSOP II package, and one 2Kb EEPROM in an 8
pin TSOP package for Serial Presence Detect which
are mounted on a 144 pin SO-DIMM multilayer FR4
Substrate.
* This product is subject to change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
Pin Front Pin Back Pin Front Pin Back Pin Back Pin Back
1 VSS 2 VSS 51 DQ14 52 DQ46 95 DQ21 96 DQ53
3 DQ0 4 DQ32 53 DQ15 54 DQ47 97 DQ22 98 DQ54
5 DQ1 6 DQ33 55 VSS 56 VSSv 99 DQ23 100 DQ55
7 DQ2 8 DQ34 57 NC 58 NC 101 VCC 102 VCC
9 DQ3 10 DQ35 59 NC 60 NC 103 A6 104 A7
11 VCC 12 VCC
105 A8 106 BA0
13 DQ4 14 DQ36 VOLTAGE KEY 107 VSS 108 VSS
15 DQ5 16 DQ37
109 A9 110 BA1
17 DQ6 18 DQ38 61 CLK0 62 CKE0 111 A10/AP 112 A11
19 DQ7 20 DQ39 63 VCC 64 VCC 113 VCC 114 VCC
21 VSS 22 VSS 65 RAS# 66 CAS# 115 DQM2 116 DQM6
23 DQM0 24 DQM4 67 WE# 68 *CKE1 117 DQM3 118 DQM7
25 DQM1 26 DQM5 69 CS0# 70 *A12 119 VSS 120 VSS
27 VCC 28 VCC 71 *CS1# 72 *A13 121 DQ24 122 DQ56
29 A0 30 A3 73 DNU 74 *CK1 123 DQ25 124 DQ57
31 A1 32 A4 75 VSS 76 VSS 125 DQ26 126 DQ58
33 A2 34 A5 77 NC 78 NC 127 DQ27 128 DQ59
35 VSS 36 VSS 79 NC 80 NC 129 VCC 130 VCC
37 DQ8 38 DQ40 81 VCC 82 VCC 131 DQ28 132 DQ60
39 DQ9 40 DQ41 83 DQ16 84 DQ48 133 DQ29 134 DQ61
41 DQ10 42 DQ42 85 DQ17 86 DQ49 135 DQ30 136 DQ62
43 DQ11 44 DQ43 87 DQ18 88 DQ50 137 DQ31 138 DQ63
45 VCC 46 VCC 89 DQ19 90 DQ51 139 VSS 140 VSS
47 DQ12 48 DQ44 91 VSS 92 VSS 141 **SDA 142 **SCL
49 DQ13 50 DQ45 93 DQ20 94 DQ52 143 VCC 144 VCC
A0 – A11
BA0-1
DQ0-63
CLK0
CKE0
CS0#
RAS#
CAS#
WE#
DQM0-7
VCC
VSS
*VREF
SDA
SCL
DNU
NC
PIN NAMES
Address input (Multiplexed)
Select Bank
Data Input/Output
Clock input
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
Power supply for reference
Serial data I/O
Serial clock
Do not use
No Connect
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
June 2006
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
www.datasheet4u.com
White Electronic Designs
WED3DG644V-D1
Parameter
AC input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
AC OPERATING TEST CONDITIONS
VCC = 3.3V ± 0.3V, 0 ≤ TA ≤ 70°C
Value
2.4/0.4
1.4
tR/tF = 1/1
1.4
Unit
V
V
ns
V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS# to CAS# delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Symbol
tRRD (min)
tRCD (min)
tRP (min)
tRAS (min)
tRAS (max)
tRC (min)
tRDL (min)
tDAL (min)
tCDL (min)
tBDL (min)
tCCD (min)
CAS latency=3
CAS latency=2
Version
7.5, 10
15
20
20
45
100
65
2
2 CLK + tRP
1
1
1
2
1
Unit
ns
ns
ns
ns
us
ns
CLK
—
CLK
CLK
CLK
ea
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Note
1
1
1
1
1
2
2
2
3
4
June 2006
Rev. 3
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet WED3DG644V-D1.PDF ] | |
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