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PDF WED3C7558M-XBX Data sheet ( Hoja de datos )

Número de pieza WED3C7558M-XBX
Descripción RISC Microprocessor Multichip Package
Fabricantes White Electronic Designs 
Logotipo White Electronic Designs Logotipo



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No Preview Available ! WED3C7558M-XBX Hoja de datos, Descripción, Manual

Whitewww.datasheet4u.com Electronic Designs
WED3C7558M-XBX
RISC Microprocessor Multichip Package
OVERVIEW
The WEDC 755/SSRAM multichip package is targeted for
high performance, space sensitive, low power systems and
supports the following power management features: doze,
nap, sleep and dynamic power management.
The WED3C7558M-XBX multichip package consists of:
755 RISC processor
Dedicated 1MB SSRAM L2 cache, configured as
128Kx72
21mmx25mm, 255 Ceramic Ball Grid Array (CBGA)
Core Frequency/L2 Cache Frequency (300MHz/
150MHz, 350MHz/175MHz)
Maximum 60x Bus frequency = 66MHz
The WED3C7558M-XBX is offered in Commercial (0°C
to +70°C), industrial (-40°C to +85°C) and military (-55°C
to +125°C) temperature ranges and is well suited for
embedded applications such as missiles, aerospace,
flight computers, fire control systems and rugged critical
systems.
* This product is subject to change without notice.
FEATURES
Footprint compatible with WED3C750A8M-200BX
Footprint compatible with Motorola MPC 745
FIGURE 1 – MULTI-CHIP PACKAGE DIAGRAM
August 2002
Rev. 7
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




WED3C7558M-XBX pdf
Whitewww.datasheet4u.com Electronic Designs
WED3C7558M-XBX
PACKAGE PINOUT LISTING
Signal Name
A[0-31]
AACK#
ABB#
AP[0-3]
ARTRY#
AVCC
BG#
BR#
BVSEL (4, 5, 6)
CI#
CKSTP_IN#
CKSTP_OUT#
CLK_OUT
DBB#
DBG#
DBDIS#
DBWO#
DH[0-31]
DL[0-31]
DP[0-7]
DRTRY#
GBL#
GND
HRESET#
INT#
L1_TSTCLK (1)
L2_TSTCLK (1)
L2AVCC (8)
L2OVCC (9)
L2VSEL (4, 5, 6, 7)
LSSD_MODE# (1)
MCP#
NC (No-connect)
OVCC (2)
PLL_CFG[0-3]
QACK#
QREQ#
RSRV#
SMI#
SRESET#
STCK (10)
STDI
STDO
Pin Number
C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, H1, E16, H2, F13, J1,
F14, J2, F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1
L2
K4
C1, B4, B3, B2
J4
A10
L1
B6
B1
E1
D8
A6
D7
J14
N1
H15
G4
P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P9, N9, T10, R9, T9,
P8, N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5, N5, T5, T4
K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16,
P15, R16, R14, T14, N10, P13, N12, T13, P3, N3, N4, R3, T1, T2, P4, T3, R4
M2, L3, N2, L4, R1, P2, M4, R2
G16
F1
C5, C12, E3, E6, E8, E9, E11, E14, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7,
H10, H12, J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9,
M11, M14, P5, P12
A7
B15
D11
D12
L11
E10, E12, M12, G12, G14, K12, K14
B5
B10
C13
C3, C6, D5, D6, H4, A4, A5, A2, A3
C7, E5, G3, G5, K3, K5, P7, P10, E7, M5, M7, M10
A8, B9, A9, D9
D3
J3
D1
A16
B14
B7
C8
J16
* Not supported on this version
Active
High
Low
Low
High
Low
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
High
High
High
Low
Low
Low
Low
High
High
High
Low
Low
High
Low
Low
Low
Low
Low
I/O 2.0V (7) 3.3V (7)
I/O
Input
I/O
I/O
I/O
Input
Output
Input
Output
Input
Ouput
Output
I/O
Input
Input
Input
I/O
2.0V
GND
2.0V
3.3V
I/O
I/O
Input
I/O
— GND GND
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
Input
Input
Output
2.0V
2.0V
*—
2.0V
3.3V
3.3V
August 2002
Rev. 7
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





WED3C7558M-XBX arduino
Whitewww.datasheet4u.com Electronic Designs
WED3C7558M-XBX
PLL POWER SUPPLY FILTERING
The AVCC and L2AVCC power signals are provided on
the WED3C7558M-XBX to provide power to the clock
generation phase-locked loop and L2 cache delay-locked
loop respectively. To ensure stability of the internal clock,
the power supplied to the AVCC input signal should be
filtered of any noise in the 500kHz to 10 MHz resonant
frequency range of the PLL. A circuit similar to the
one shown in Figure 6 using surface mount capacitors
with minimum Effective Series Inductance (ESL) is
recommended. Multiple small capacitors of equal value
are recommended over a single large value capacitor.
The circuit should be placed as close as possible to the
AVCC pin to minimize noise coupled from nearby circuits.
An identical but separate circuit should be placed as close
as possible to the L2AVCC pin. It is often possible to route
directly from the capacitors to the AVCC pin, which is on the
periphery of the 255 BGA footprint, without the inductance
of vias. The L2AVCC pin may be more difficult to route but
is proportionately less critical.
FIGURE 6 – POWER SUPPLY FILTER CIRCUIT
10
Vcc
AVcc (or L2AVcc)
2.2 µF
2.2 µF
Low ESL surface mount capacitors
GND
August 2002
Rev. 7
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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