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PDF WED3C7410E16M-400BX Data sheet ( Hoja de datos )
| Número de pieza | WED3C7410E16M-400BX | |
| Descripción | RISC Microprocessor Multichip Package | |
| Fabricantes | White Electronic Designs | |
| Logotipo |  |
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Whitewww.datasheet4u.com Electronic Designs WED3C7410E16M-400BX
RISC Microprocessor Multichip Package *PRELIMINARY
OVERVIEW
The WED3C7410E16M-400BX is offered in Commercial (0°C
The WEDC 7410E/SSRAM multichip package is targeted for
high performance, space sensitive, low power systems and
supports the following power management features: doze,
nap, sleep and dynamic power management.
to +70°C), industrial (-40°C to +85°C) and military (-55°C
to +125°C) temperature ranges and is well suited for em-
bedded applications such as missiles, aerospace, flight
computers, fire control systems and rugged critical systems.
The WED3C7410E16M-400BX multichip package consists
of:
*This data sheet describes a product that is developmental, is not qualified or
characterized and is subject to change without notice.
• 7410E AltiVec RISC processor
• Dedicated 2MB SSRAM L2 cache, configured as
256Kx72
FEATURES
n Footprint compatible with WED3C7558M-XBX and
• 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA)
• Maximum Core frequency = 400MHz @ 1.8V
• Maximum L2 Cache frequency = 200MHz
WED3C750A8M-200BX
n Implementation of Altivec technology instruction set
n Optional, high-bandwidth MPX bus interface
• Maximum 60x Bus frequency = 100MHz
FIG. 1 MULTI-CHIP PACKAGE DIAGRAM
AltiVec is a trademark of Motorola Inc.
October 2002 Rev. 5
1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
1 page  
Whitewww.datasheet4u.com Electronic Designs WED3C7410E16M-400BX
Signal Name
A[0-31]
A ACK
ABB/AMONO (8)
AP[0-3]
ARTRY
AVDD
BG
BR
BVSEL (4, 6)
CHK (5, 6, 13)
CI
CKSTP_IN
CKSTP_OUT
CLK_OUT
DBB/DMONO (8)
DBG
DBWO/DTI[0]
DH[0-31]
DL[0-31]
DP[0-7]
DRDY (5, 9, 12)
DTI 1-2 (9, 11)
EMODE (10, 11)
GBL
GND
HIT (5) (12)
HRESET
INT
L1_TSTCLK (1)
L2_TSTCLK (1)
L2AVDD
L2VDD (5) (7)
L2OVDD
L2VSEL (3, 6)
LSSD_MODE (1)
MCP
NC (No-connect)
OVDD (2)
PLL_CFG[0-3]
QACK
QREQ
RSRV
SHD0-1 (5) (14)
SMI
SRESET
PACKAGE PINOUT LISTING
Pin Number
C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, H1, E16, H2, F13, J1, F14,
J2, F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1
L2
K4
C1, B4, B3, B2
J4
A10
L1
B6
B1
C6
E1
D8
A6
D7
J14
N1
G4
P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P9, N9, T10, R9, T9, P8,
N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5, N5, T5, T4
K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15,
R16, R14, T14, N10, P13, N12, T13, P3, N3, N4, R3, T1, T2, P4, T3, R4
M2, L3, N2, L4, R1, P2, M4, R2
D5
G16, H15
C4
F1
C5, C12, E3, E6, E8, E9, E11, E14, F3, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7, H10, H12,
J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5, P12
A3
A7
B15
D11
D12
L11
A2, B8, C3, D6, J16
E10, E12, M12, G12, G14, K12, K14
B5
B10
C13
B7, C8
C7, E5, G3, G5, K3, K5, P7, P10, E7, M5, M7, M10
A8, B9, A9, D9
D3
J3
D1
A4, A5
A16
B14
Active
High
Low
Low
High
Low
—
Low
Low
High
Low
Low
Low
Low
High
Low
Low
Low
High
High
High
Low
High
Low
Low
—
Low
Low
Low
High
High
—
—
—
High
Low
Low
—
—
High
Low
Low
Low
Low
Low
Low
I/O 1.8V (7) 2.5V (7) 3.3V (7)
I/O
Input
Output
I/O
I/O
Input
Input
Output
Input
Input
I/O
Input
Ouput
Output
Output
Input
Input
I/O
1.8V 1.8V 1.8V
GND HRESET OVDD
I/O
I/O
Output
Input
Input
I/O
—
GND GND
GND
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
—
Input
Input
Input
Output
Output
I/O
Input
Input
1.8V 1.8V 1.8V
3.3V 3.3V 3.3V
2.5V N/A
*— HRESET N/A
3.3V
1.8V 2.5V 3.3V
5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
5 Page 
Whitewww.datasheet4u.com Electronic Designs WED3C7410E16M-400BX
PLL POWER SUPPLY FILTERING
The AVdd and L2AVdd power signals are provided on
The circuit should be placed as close as possible to the
the WED3C7410E16M-400BX to provide power to the
AVdd pin to minimize noise coupled from nearby
clock generation phase-locked loop and L2 cache
circuits. An identical but separate circuit should be
delay-locked loop respectively. To ensure stability of
placed as close as possible to the L2AVdd pin. It is
the internal clock, the power supplied to the AVdd
often possible to route directly from the capacitors to
input signal should be filtered of any noise in the
the AVdd pin, which is on the periphery of the 255 BGA
500kHz to 10 MHz resonant frequency range of the
footprint, without the inductance of vias. The L2AVdd
PLL. A circuit similar to the one shown in Figure 6
pin may be more difficult to route but is proportionately
using surface mount capacitors with minimum Effective
less critical.
Series Inductance (ESL) is recommended. Multiple
small capacitors of equal value are recommended over
a single large value capacitor.
FIG. 6 POWER SUPPLY FILTER CIRCUIT
10 Ω
Vdd
2.2 µF
GND
AVdd (or L2AVdd)
2.2 µF
Low ESL surface mount capacitors
1 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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