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PDF MAX1147 Data sheet ( Hoja de datos )

Número de pieza MAX1147
Descripción (MAX1146 - MAX1149) 14-Bit ADCs
Fabricantes Maxim Integrated Products 
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No Preview Available ! MAX1147 Hoja de datos, Descripción, Manual

19-3488; Rev 2; 1/07
EVAALVUAAILTAIOBNLEKIT
Multichannel, True-Differential,
Serial, 14-Bit ADCs
General Description
The MAX1146–MAX1149 low-power, 14-bit, multichan-
nel, analog-to-digital converters (ADCs) feature an
internal track/hold (T/H), voltage reference, and clock.
The MAX1146/MAX1148 operate from a single +4.75V
to +5.25V supply, and the MAX1147/MAX1149 operate
from a single +2.7V to +3.6V supply. All analog inputs
are software configurable for unipolar/bipolar and sin-
gle-ended/differential operation.
The 4-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. The serial strobe output (SSTRB) allows conve-
nient connection to digital signal processors. The
MAX1146–MAX1149 use an internal clock or an exter-
nal serial-interface clock to perform successive-approx-
imation analog-to-digital conversions.
The MAX1146/MAX1148 include an internal +4.096V
reference, while the MAX1147/MAX1149 include an
internal +2.500V reference. All devices accept an exter-
nal reference from 1.5V to VDD.
The MAX1146–MAX1149 provide a hardware shutdown
and two software power-down modes. Using the soft-
ware power-down modes allows the devices to be pow-
ered down between conversions. When powered down,
accessing the serial interface automatically powers up
the devices. The quick turn-on time allows power-down
between all conversions. This technique reduces sup-
ply current to under 120µA for quick turn-on.
The MAX1146–MAX1149 are available in a 20-pin
TSSOP package.
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Process Control
Features
8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1148/MAX1149)
4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1146/MAX1147)
Internal Multiplexer and T/H
Single-Supply Operation
4.75V to 5.25V Supply (MAX1146/MAX1148)
2.7V to 3.6V Supply (MAX1147/MAX1149)
Internal Reference
+4.096V (MAX1146/MAX1148)
+2.500V (MAX1147/MAX1149)
116ksps Sampling Rate
Low Power
1.1mA (116ksps)
120µA (10ksps)
12µA (1ksps)
300nA (Power-Down Mode)
SPI-/QSPI-/MICROWIRE Compatible
20-Pin TSSOP
Pin Configurations appear at end of data sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PART
MAX1146BCUP
MAX1146BEUP
MAX1147BCUP
MAX1147BEUP
MAX1148BCUP
MAX1148BEUP
MAX1149BCUP
MAX1149BEUP
TEMP
RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-
PACKAGE
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
Ordering Information/Selector Guide
INL
(LSB)
±2
±2
±2
±2
±2
±2
±2
±2
INPUT
CHANNELS
4
4
4
4
8
8
8
8
INTERNAL
REFERENCE (V)
+4.096
+4.096
+2.500
+2.500
+4.096
+4.096
+2.500
+2.500
PKG
CODE
U20-3
U20-3
U20-3
U20-3
U20-3
U20-3
U20-3
U20-3
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

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MAX1147 pdf
Multichannel, True-Differential,
Serial, 14-Bit ADCs
TIMING CHARACTERISTICS
(VDD = 4.75V to 5.25V (MAX1146/MAX1148), VDD = 2.7V to 3.6V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz,
external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF
for the MAX1146/MAX1148, external 2.500V reference at REF for the MAX1147/MAX1149, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.) (Figures 1, 2, and 3)
PARAMETER
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Fall to Output Data Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
SHDN Rise CS Fall to SCLK Rise
Time
SHDN Rise CS Fall to SCLK Rise
Hold Time
SCLK Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SSTRB Output Enable
CS Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
SCLK Fall to SSTRB Edge
CS Pulse Width
SYMBOL
tDS
tDH
tDOV
tDOE
tDOD
tCSS
tCSH
fSCLK
tCH
tCL
tSTE
tSTD
tSCK
tSCST
tCSW
CONDITIONS
CLOAD = 50pF
CLOAD = 50pF
CLOAD = 50pF
External clock mode
Internal clock mode
Internal clock mode
Internal clock mode
External clock mode only
External clock mode only
Internal clock mode only
MIN TYP MAX UNITS
50 ns
0 ns
10 80 ns
120 ns
120 ns
50 ns
50 ns
0.1 2.1
MHz
0 2.1
100 ns
100 ns
120 ns
120 ns
0 ns
80 ns
100 ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Tested at VDD = 3.0V (MAX1147/MAX1149) or 5.0V(MAX1146/MAX1148); VCOM = 0; unipolar single-ended input mode.
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Offset nulled. Measured with external reference.
“On” channel grounded; full-scale 1kHz sine wave applied to all “off” channels.
Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. (See
Figures 8–11.)
The common-mode range for the analog inputs is from AGND to VDD.
Digital inputs equal VDD or DGND.
External load should not change during conversion for specified accuracy.
Measured as (VFS x 3.6V) - (VFS x 2.7V) for the MAX1147/MAX1149 and (VFS x 5.25V) - (VFS x 4.75V) for the
MAX1146/MAX1148. VDD = 3.6V to 2.7V for MAX1147/MAX1149 and VDD = 5.25V to 4.75V for the MAX1146/MAX1148.
_______________________________________________________________________________________ 5

5 Page





MAX1147 arduino
Multichannel, True-Differential,
Serial, 14-Bit ADCs
Pin Description
PIN
MAX1148 MAX1146
MAX1149 MAX1147
NAME
FUNCTION
1 1 CH0
2 2 CH1
3 3 CH2
4 4 CH3
Analog Inputs
5 — CH4
6 — CH5
7 — CH6
8 — CH7
9
9
COM
Common Input. Negative analog input in single-ended mode. COM sets zero-code voltage in
unipolar and bipolar mode.
10 10 SHDN Active-Low Shutdown Input. Pulling SHDN low shuts down the device reducing supply current
to 0.2µA. Driving shutdown high enables the devices.
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital
11 11 REF conversion. In internal reference mode, the MAX1146/MAX1148 VREF is +4.096V, and the
MAX1147/MAX1149 VREF is +2.500V.
Bandgap Reference Output and Reference Buffer Input. Bypass to AGND with a 0.01µF
12 12 REFADJ capacitor. Connect REFADJ to VDD to disable the internal bandgap reference and reference-
buffer amplifier.
13 13 AGND Analog Ground
14 14 DGND Digital Ground
15
15
DOUT
Serial Data Output. Data is clocked out at the falling edge of SCLK when CS is low. DOUT is
high impedance when CS is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC conversion
16
16
SSTRB
begins, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for two clock periods before the MSB decision. SSTRB is high impedance when CS is high
(external clock mode).
17
17
DIN
Serial Data Input. Data is clocked in at the rising edge of SCLK when CS is low. DIN is high
impedance when CS is high.
18 18 CS Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
19 19 SCLK Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed
in external clock mode. (Duty cycle must be 40% to 60%.)
20 20 VDD Positive Supply Voltage. Bypass to AGND with a 0.1µF capacitor.
— 5–8 N.C. No Connection. Not internally connected.
______________________________________________________________________________________ 11

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