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PDF SAE81C80A Data sheet ( Hoja de datos )
| Número de pieza | SAE81C80A | |
| Descripción | CMOS Dual Port RAM | |
| Fabricantes | Siemens | |
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CMOS Dual-Port RAM
SAE 81C80 A
CMOS IC
Features
q Processor interface with address and data bus
plus signals ALE, WR, RD
q 8051-, 8096-compatible timing
q Memory capacity 504 bytes
q All functions fully static (excl. oscillator watchdog)
q Standby operation
q On-chip oscillator with separate clock output
q Eight scheduling registers
q Three loadable timers for processor monitoring or
applicable as longterm timers
q Monitoring of internal oscillator
(hardware watchdog)
q Three outputs for interrupt triggering
(can be set on the bus)
q Fully asynchronous operation of two processors
possible
q Data retention down to 1 V
q P-LCC-44 (SMD) package
q Extended temperature range from – 40 through
110 °C
q CMOS technology
Type
SAE 81C80 A
Ordering Code
Q67100-H8706
P-LCC-44-1
Package
P-LCC-44-1 (SMD)
The SAE 81C80 A dual-port RAM (DPR) is a CMOS memory IC with a capacity of 504
bytes (figure 1).
A very notable feature of this DPR is that it can be used by two microcontrollers (MCs)
simultaneously and fully asynchronously. Each microcontroller uses the DPR like a
normal static RAM. Thus, when comparing the circuit development of this DPR with that
of standard memory, no extra effort is required. Access collisions are excluded, which is
the pre-requisite for fast communication between the two MCs.
The SAE 81C80 A DPR is ideally suited for multi-processor/multi-controller applications
like master/slave configurations or controls where one controller aquires measured data
and a second one controls the actuators (e.g. in motors, etc.). (See figures 2 and 3).
Semiconductor Group
1
09.94
1 page  
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SAE 81C80 A
Figure 1
Principle of the Dual-Port-RAM (DPR)
Semiconductor Group
5
5 Page 
SAE 81C80 A
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Only for the registers of timers 1 and 2
Bit 1-3: These are used together with bit 0 for switching the watchdog mode ON and
OFF.
Only for the register of timer 3
Bit 1-2: Reserved (should always be 0 for correct operation).
Bit 3: Switches all three timers to test mode, i.e. only the upper twelve bits are used
to generate the output signal (reset state = 0).
Watchdog Mode
For timers 1 and 2 a special mode was implemented which can be used to monitor the
two processors. In this mode there is a control register (CR) for each timer (see table 1
for addresses). The watchdog mode is set by loading the TMR with the value
101X1111B, the polarity of the output signal being freely selectable with bit 4. This mode
works similarly to the auto-reload mode, but neither the reload register nor the TMR can
be altered.
In the watchdog mode, the timer can only be restarted (and the output pulse suppressed)
if the values 055H and 0AAH are successively written into the control register. The time
between these two write operations is random, but the sequence must be completed
before the timer has run down, i.e. the output pulse is generated. No value may be
written into either the TMR or CR between the two write operations, otherwise the
sequence has to be started again.
To reset the timer to the normal mode, first the value 055H has to be written into the CR,
then the value 010X0000B into the TMR, and finally the value 0AAH into the CR. Here,
too, if any other value is written into either of the two registers during the sequence, the
entire operation has to be started again. The time between the accesses is random.
The timer operation in watchdog mode is illustrated in the appendix in an 8051 example
program.
Note: The relevant bits for changing the timer state to watchdog mode are bit 0 - bit 3;
the shown pattern is the only one, which makes sense for this mode.
Semiconductor Group
11
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