|
|
PDF ICS8432-51K Data sheet ( Hoja de datos )
| Número de pieza | ICS8432-51K | |
| Descripción | CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS8432-51K (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
Integrated
Circuit
www.DataSheet4US.ycosmtems, Inc.
PRELIMINARY
ICS8432-51K
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
ICS
The ICS8432-51K is a general purpose, dual out-
put Crystal-to-3.3V Differential LVPECL High Fre-
HiPerClockS™ quency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8432-51K has a se-
lectable TEST_CLK or crystal input. The VCO operates at a
frequency range of 250MHz to 700MHz. The VCO frequency
is programmed in steps equal to the value of the input reference
or crystal frequency. The VCO and output frequency
can be programmed using the serial or parallel interface to
the configuration logic. The low phase noise characteristics
of the ICS8432-51K make it an ideal clock source for Gigabit
Ethernet, Fibre Channel 1 and 2, and Infiniband applications.
FEATURES
• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface or
LVCMOS/LVTTL TEST_CLK
• Output frequency range: 31.25MHz to 700MHz
• Crystal input frequency range: 12MHz to 25MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 3.5ps (maximum)
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Replaces the ICS8432-01
BLOCK DIAGRAM
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL1
XTAL2
OSC
0
1
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
PLL
PHASE DETECTOR
VCO
0
÷1
÷2
÷M
÷4
1 ÷8
CONFIGURATION
INTERFACE
LOGIC
PIN ASSIGNMENT
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
32 31 30 29 28 27 26 25
M5 1
M6 2
M7 3
M8 4
N0 5
N1 6
nc 7
ICS8432-51K
24 XTAL2
23 TEST_CLK
22 XTAL_SEL
2 1 VCCA
20 S_LOAD
19 S_DATA
18 S_CLOCK
VEE 8
17 MR
9 10 11 12 13 14 15 16
32-Lead VFQFN
5mm x 5mm x 0.95m package body
K Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8432BK-51
www.icst.com/products/hiperclocks.html
REV. A MARCH 22, 2004
1
1 page  
Integrated
Circuit
www.DataSheet4US.ycosmtems, Inc.
PRELIMINARY
ICS8432-51K
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, VI
Outputs, IO
Continuous Current
Surge Current
Package Thermal Impedance, θJA
Storage Temperature, T
STG
4.6V
-0.5V to VCC + 0.5 V
50mA
100mA
41.07°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VCC
VCCA
VCCO
IEE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
135
15
Units
V
V
V
mA
mA
TABLE
4B.
LVCMOS
/
LVTTL
DC
CHARACTERISTICS,
V
CC
=
V
CCA
=
V
CCO
=
3.3V±5%,
TA
=
0°C
TO
70°C
Symbol
VIH
VIL
I
IH
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
TEST_CLK
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
TEST_CLK
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
M5, XTAL_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
IIL
Input
S_DATA, S_LOAD, nP_LOAD
Low Current
M5, XTAL_SEL, VCO_SEL
VOH
Output
High Voltage
TEST; NOTE 1
Test Conditions
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V,
VIN = 0V
VCC = 3.465V,
VIN = 0V
Minimum Typical Maximum Units
2
VCC + 0.3
V
2
VCC + 0.3
V
-0.3 0.8 V
-0.3 1.3 V
150 µA
5 µA
-5 µA
-150
2.6
µA
V
VOL
Output
Low Voltage
TEST; NOTE 1
NOTE 1: Outputs terminated with 50Ω to VCCO/2.
0.5 V
8432BK-51
www.icst.com/products/hiperclocks.html
5
REV. A MARCH 22, 2004
5 Page 
Integrated
Circuit
www.DataSheet4US.ycosmtems, Inc.
PRELIMINARY
ICS8432-51K
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
• The differential 50Ω output traces should have the
same length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL2) and 25 (XTAL1). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
C1
U1
PIN 1
C2
X1
C11
R7
C16
VCCA
GND
VCC
VIA
Close to the input
pins of the
receiver
8432BK-51
C15
C14
TL1 R1
R2
TL1N
TL1, TL21N are 50 Ohm
traces and equal length
R3
R4
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8432-51K
www.icst.com/products/hiperclocks.html
11
REV. A MARCH 22, 2004
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS8432-51K.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS8432-51K | CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER | Integrated Circuit Systems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |