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PDF U3550BM Data sheet ( Hoja de datos )

Número de pieza U3550BM
Descripción Low-Power FM Transmitter / Synthesizer System 26 to 50 MHz
Fabricantes TEMIC Semiconductors 
Logotipo TEMIC Semiconductors Logotipo



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U3550BM
Low-Powerwww.DataSheet4U.com FM Transmitter / Synthesizer System 26 to 50 MHz
Description
The U3550BM is a radio-frequency IC for analog
cordless telephone applications in the 26/50-MHz band
(CTO standard). The IC performs full duplex communi-
cation. The transmitting and receiving frequency depends
on whether the IC is used in the handset or in the base
station.
The U3550BM’s frequency converter consists of an FM
transmitter with switchable output power and receiver
Mixer 1 in the same unit. A two-wire bus interface can be
used for frequency control as well as for switching the
transmitter’s power amplifier and the receiver. Fine
frequency adjustment of the reference crystal oscillator is
programmable.
The receive part is designed for a double-conversion
architecture. The incoming radio-frequency signal will
be filtered and amplified before reaching the first mixer.
At this stage, the RF signal will be converted down to the
first intermediate frequency (10.7 MHz) by using a local
adjustable oscillator (VCO3). The frequency of this
oscillator is controlled by the PLL.
The transmitter part contains two PLL-controlled VCOs.
The frequency modulation is accomplished by
superposing the incoming audio signal on the first PLL
control voltage. In this system, the frequency is a product
of mixing VCO1 with local oscillator (VCO3). The FM-
modulated carrier is amplified by external power
amplifier before entering the output filter and the antenna
connector.
Features
D All PLLs and most of the oscillators are integrated
D All functions and channel selection controllable by
serial bus
D Receiver Mixer 1 with integrated image rejection
D Up to 25 channels selectable depending on CT0
standard
D Integrated oscillator circuit with external crystal
(11.15 MHz)
D Programmable carrier-modulation frequency
Application
D CT0 (USA, France, Spain, Netherlands, Portugal,
Korea, Taiwan, New Zealand, China)
D Narrowband voice and data transmitting / receiving
systems
Block Diagram
VBAT DELVB DELGND MIXO LOGND PCLO
OSCVDD MCKA OSCGND
VCC
MIXIN
MIXVB
LO1
LO2
VTX
RFOVB
RFO
RFOGND
Mixer 1
+ 45
– 45
10.7 MHz
sin
VCO 3
sin
cos
2
cos
Mixer 2
+ 45
– 45
N
Phase
comparator
11.15 MHz Oscillator
interface
K 20
557.5 KHz
Serial BUS
interface
XCK
MCKO
C
D
D 1 D 2 VCO 1
2
D3
P
GREF
VCO 2
Loop
filter
Phase
comparator
Phase
comparator
LFGND
AGND
VSS
MODIN
Figure 1. Block diagram
MLF
13280
Rev. A2, 10-Sep-98
Preliminary Information
1 (25)

1 page




U3550BM pdf
U3550BM
wwwM.DaotadShueleat4tUo.cromPLL
The fractional divider has been chosen to increase
+ ń ǒ ) Ǔreference the frequency of the modulator PLL.
Q
557.5 kHz fmod P 223
P: integer part of the fractional divider
+ ǒ ǓQ: fractional part of the fractional divider
Q 223
fmod
557.5 kHz
–P
+223
557.7 kHz
2.5 kHz
The frequency step 2.5 kHz is a fraction of the reference
frequency 557.5 kHz
³ ) ) + )Qx (P 1) (223–Q)P
223
P
Q
223
For each comparison cycle (fRef1 = 557.5 kHz), the accu-
mulator content is incremented by the Q value and the
divider divides by the P value. When the accumulator
value reaches or exceeds 223, the divider divides by the
value (P + 1). Then, the accumulator holds the excess
value (accumulator value – 223). After 223 cycles, the
correct division is executed.
Local Oscillator PLL
+fRef3
fLO
N
Serial Bus Interface
The circuit is remoted by an external microcontroller
through the serial bus.
The data is a 12-bit word:
A0 – A3: address of the destination register (0 to 15)
D0 – D7: contents of register
The data line must be stable when the clock is high and
data must be shifted serially.
After a 12-clock period, the transfer to the destination
register is generated (internally) by a low-to-high
transition of the data line when the clock is high.
Micro-
processor
Data
Clock
Figure 4.
D
C
96 11787
Data
(D)
Clock
(C)
13279
D0 D1 D2
A0 A1 A2 A3
1st word
Word transmission
Figure 5. Serial bus transmission
2nd word
Transfer condition
Rev. A2, 10-Sep-98
Preliminary Information
5 (25)

5 Page





U3550BM arduino
U3550BM
www.DataSheePta4rUam.ceotemrs
Third order input intercept point
Image-frequency rejection
Test Conditions / Pins
M1CP = 0
W M1CP = 1
50- input impedance
FRF1 = 41.4 MHz
FRF2 = 41.4125 MHz
Input level 1 = –30 dBm
Input level 2 = –30 dBm
Fb8: fLO = 30.7 MHz
UDM1 = 0
FRF11 = 41.4 MHz
FRF12 = 20 MHz (image)
Symbol
Min.
Typ.
Max.
Unit
–7 –5
–4 –2
dBm
dBm
20 dB
Fb8: fLO = 30.7 MHz
UDM1 = 0
FRF21 = 20 MHz
FRF22 = 41.4 MHz (image)
LO to RF MIXIN input isolation
LO to IF MIXO output isolation
Isolation transmit path to receive
path (crosstalk)
Logical part
Inputs: C, D
Low-voltage input
High-voltage input
Inputs: C, D, MCKA
Input leakage current
(0 < VI < VCC)
Input leakage current Pin XCK
(0 < VI < VCC)
Output impedance at MCKO
Serial bus (figure 8)
Data set-up rime
Data hold time
Clock low time
Clock high time
Hold time before transfer
condition
Data low pulse on transfer
condition
Data high pulse on transfer
condition
Fb8: fLO = 57.67 MHz
UDM1 = 1
FRF31 = 46.97 MHz
FRF32 = 68.37
Fb8: measuring, fLO = 30.7 MHz
Fb8: measuring, fLO = 30.7 MHz
Synthesizer programming
as ‘Taiwan channel 5’ (see page 21),
transmitter modulation (Pin 25) for
Df = 3 kHz, fmod = 300 to 3400 kHz,
M1CP = 1,
WfRF (Pin 10) = 45.35 or 48.35 MHz
unmodulated, –25 dBm (50 ) measuring
frequency modulation of the 10.7 MHz
signal at MIXO (Pin 12)
(1) IS = IVBAT + IVCC + IMIXVB + IRFOVB
+ ODELVB + I1OSCVDD
(2) 1-measure 11.15 MHz at MCKO pin
2-measure FRFO at RFO pin
(3)
(4)
0.2 mVrms
1.2 mVrms
28 dB
Vil
Vih 0.8 VCC
Vi –1
–5
0.5
tsud 0.1
thd 0
tcl 2
tch 2
teon 0.1
teh 0.2
teoff 0.2
0.2 VCC
1
5
1.0
mA
mA
kW
mmss
ms
ms
ms
ms
ms
See country channels
Ratio between demodulated audio level with and
without 1-kHz modulation
Rev. A2, 10-Sep-98
Preliminary Information
11 (25)

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