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PDF RTL8186P Data sheet ( Hoja de datos )

Número de pieza RTL8186P
Descripción Wireless LAN Access Point/Gateway Controller
Fabricantes Realtek 
Logotipo Realtek Logotipo



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RTL8186/RTL8186P
WIRELESS LAN ACCESS POINT/
GATEWAY CONTROLLER
Preliminary DATASHEET
Rev. 0.9
4 Aug 2004
Track ID: XXXXXXXXX

1 page




RTL8186P pdf
wwnw.Data1S6-heenettr4yUM.coMmU supported
n Up to 200MHZ operating frequency
RTL8186
WLAN Controller
n Integrated IEEE 802.11a/b/g complied MAC and DSSS Baseband processor
n Data rate of 54M, 48M, 36M, 24M, 18M, 12M, 9M, 6M, 11M, 5.5M, 2M and 1M
n Support antenna diversity and AGC
n Support 802.11h DFS and TPC
n Embedded with encryption/decryption engine for 64 bits/128 bits WEP, TKIP/MIC and AES
n RF interface to Realtek 2.4G and 5G RF module
Fast Ethernet Controller
n Fully compliant with IEEE 802.3/802.3u
n Supports MII interface with full and half duplex capability
n Supports descriptor-based buffer management with scatter-gather capability
n Supports IP, TCP, and UDP checksum offload
n Supports IEEE 802.1Q VLAN tagging and 802.1P priority queue
n Supports full duplex flow control (IEEE 802.3X)
UART
n 2 UART interfaces
n 16550 compatible
n 16 bytes FIFO size
n Auto CTS/RTS flow control
Memory Controller
n Supports external 16/32-bit SDRAM with 2 banks access, up to 32M bytes for each bank
n Supports two external 16-bit NOR-type Flash memory, up to 8M bytes for each bank
n Supports two external 8-bit NAND-type Flash memory, up to 32M bytes for each bank
n Support boot from NAND type to reduce total bone cost
IPSEC Crypto Engine
n Supports DES, 3DES and AES-128 encryption/decryption algorithm for ESP encryption with throughput up to 120Mbps
n Supports HMAC-MD5 and HMAC-SHA-1 authentication algorithms
n Supports CBC or EBC mode with DES/3DES/AES algorithm
n A 32-bit PRNG (pseudo random number generator)
n Single pass for both authentication and encryption/decryption
PCI Bridge
n Complies with PCI 2.2.
n Supports four external PCI devices.
n Supports PCI master/slave mode with shared IRQ
n 3.3 and 5V I/O tolerance
n One of the PCI device supports memory mapping space up to 16M bytes, others up 1M bytes
GPIO
n 11 dedicate programmable I/O ports and 58 shared GPIO ports
n Individually configurable to input, output and edge transition
Watchdog/Timer/Counter
n Hardware watchdog timer, used to reset the processor if the system hangs.
n 4 sets of general timers/counter
EJTAG
n Use standard IEEE 1149.1 JTAG interface for software debugging
CONFIDENTIAL
5 PRELIMINARY v0.9

5 Page





RTL8186P arduino
RTL8186
wwRwI.FDSatDaSPIhNeet4U.com I/O
RFLEPIN
O
62
63
R20 Serial Data Input/Output.
R18 Serial Enable control.
CALENPIN
O 68
L20 Serial Read/Write control.
CALMODEPIN I/O 59
T20 Not used in 8225 RF chipset.
VCOPDNPIN
O 74
L18 This pin is used to turn on/off RF transceiver.
TRSWPIN
O 57
R17 Transmit/Receive path select.
TRSWBPIN
O 75
M17 The TRSW select signal controls the direction of the Transmit/Receive
switch.
RFTXENPIN
O 129
C10 Not used in 8225 RF chipset.
RFRXENPIN
O 55
T18 Not used in 8225 RF chipset.
LNAHLPIN
O 117
A16 Not used in 8225 RF chipset.
ANTSELPIN
O 147
A1 Antenna Select.
ANTSELBPIN
O 152
D5 The antenna detects signal change states as the receiver switches from
antenna to antenna during the acquisition process in antenna diversity
mode.
A_PAPEPIN
O 157
F4 2.4GHz Transmit Power Amplifier Power Enable.
B_PAPEPIN
O 158
C1 Not used in 8225 RF chipset.
WLGPIOPIN[0] I/O 52
T17 General purpose input/output pin.
WLGPIOPIN[1] I/O 70
M19 General purpose input/output pin.
WLGPIOPIN[2] I/O 71
K19 General purpose input/output pin.
WLGPIOPIN[3] I/O 159
F3 General purpose input/output pin.
WLGPIOPIN[4] I/O 119
A15 General purpose input/output pin.
WLGPIOPIN[5] I/O 148
A2 General purpose input/output pin.
WLGPIOPIN[6] I/O 82
D20 General purpose input/output pin.
RF Interface for Realtek 8255 [802.11 a/b/g RF]
VREFO
X 113
A19 Not used in 8255 RF chipset.
VRP
X 112
B17 Not used in 8255 RF chipset.
VRN
X 111
C15 Not used in 8255 RF chipset.
RXIP
I 110
D14 Receive (Rx) In-phase Analog Data.
RXIN
I 109
C14
RXQP
I 107
B18 Receive (Rx) Quadrature-phase Analog Data.
RXQN
R15K
106
I/O 100
C17
D17 This pin must be pulled low by a 15K Ω resistor.
RXAGC
O 97
D18 Not used in 8255 RF chipset.
TXAGC
O 96
C18 Not used in 8255 RF chipset.
RSSI
I 95
D19 Analog Input to the Receive Power A/D Converter for Receive AGC
Control.
TSSI0
I 94
A20 Input to the Transmit Power A/D Converter for 2.4GHz Transmit AGC
Control.
TSSI1
I 93
B20 Input to the Transmit Power A/D Converter for 5GHz Transmit AGC
Control.
TXQP
O 90
H18 Transmit (TX) Quadrature-phase Analog Data.
TXQN
O 89
G18
TXIN
O 88
G19 Transmit (TX) In-phase Analog Data.
TXIP
O 87
H19
XI
I 81
H20 40 MHz OSC Input.
XIPWRSEL
I 104
B19 Operating frequency voltage selection between 3.3v and 1.8v.
TXQTP
O 86
F19 Not used in 8255 RF chipset.
TXQTN
O 85
F18
TXITP
O 84
J18 Not used in 8255 RF chipset.
TXITN
O 83
E19
RIFSCKPIN
O 61
P17 Serial Clock Output.
All operation mode switching and register setting is done by 3-wire serial
interface.
RIFSDPIN
I/O 62
R20 Serial Data Input/Output.
RFLEPIN
O 63
R18 Serial Enable control.
CALENPIN
O 68
L20 Not used in 8255 RF chipset.
CONFIDENTIAL
11 PRELIMINARY v0.9

11 Page







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