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PDF TDC1016 Data sheet ( Hoja de datos )

Número de pieza TDC1016
Descripción Video Speed D/A Converter
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! TDC1016 Hoja de datos, Descripción, Manual

TDC1016www.DataSheet4U.com
Video Speed D/A Converter
10-Bit, 20 Msps
www.fairchildsemi.com
Features
• 20 Msps conversion rate
• 8, 9, or 10-bit linearity
• Voltage output, no amplifier required
• Single supply operation (-5.2V, ECL compatible)
• Dual supply operation (±5.0V, TTL compatible)
• Internal 10-bit latched data register
• Low glitch energy
• Disabling controls, forcing full-scale, zero, and inverting
input data
• Binary or two’s complement input data formats
• Differential gain = 1.5%, differential phase = 1.0°
Applications
• Construction of video signals from digital data 3x or 4x
NTSC or PAL color subcarrier frequency
• CRT graphics displays, RGB, Raster, Vector
• Waveform synthesis
Description
The TDC1016 is a bipolar monolithic digital-to-analog
converter which can convert digital data into an analog volt-
age at rates up to 20 Msps (Megasamples Per Second). The
device includes an input data register and operates without
an external deglitcher or amplifier.
Operating the TDC1016 from a single -5.2V power supply
will bias the digital inputs for ECL levels, while operating
from a dual ±5V power supply will bias the digital inputs for
TTL levels.
All versions of the TDC1016 are 10-bit digital-to-analog
converters, but are available with linearity specifications of
either 8, 9, or 10 bits. The TDC1016 is patented under U.S.
patent number 3283120 with other patents pending.
Block Diagram
10 TTL INPUTS
(20 ECL INPUTS)
CLK
(CLK)
NDIS
(NDIS)
NFL
NFH
N2C
VREF
COMP
TTL/ECL
DIGITAL
INPUT
BUFFERS
10
DATA
CURRENT
R–2R
LATCHED
SWITCHES
RESISTOR
NETWORK
10 10
CLK VREF
A
65-1016-01
AOUT
Rev. 1.0.0

1 page




TDC1016 pdf
PRODUCT SPECIFICATION
TDC1016
Operating Conditions
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Temperature Range
Standard
Extended
Symbol Parameter
Min. Nom. Max. Min. Nom. Max.
VCC
Positive Supply Voltage
TTL Mode 4.75 5.0 5.25 4.50 5.0 5.50
ECL Mode -0.25 0.0 0.25 -0.25 0.0 0.25
VEE Negative Supply Voltage
-4.5 -5.0 -5.5 -4.5 -5.0 -5.5
VAGND Analog Ground Voltage (Measured to
DGND)
-0.1 0.0 0.1 -0.1 0.0 0.1
tPWL
CLK Pulse Width, LOW
15 20
tPWH
CLK Pulse Width, HIGH
15 20
tS Input Register Set-up Time TTL Mode 20
22
ECL Mode 25
27
tH Input Register Hold Time
2
VIL Logic 0
TTL Mode DGND
ECL Mode
VIH Logic 1
TTL Mode 2.0
ECL Mode -1.0
0.8
-1.67
VCC
2
DGND
2.01
-1.0
0.8
-1.67
VCC
VREF
CCOMP
TA
TC
Reference Voltage
Compensation Capacitor
Ambient Temperature
Case Temperature
-0.8 -1.0 -1.2 -0.8 -1.0 1.2
1.0 1.0
0 70
-55 125
Note:
1. VIH/NDIS = 2.2 Min.
Unit
V
V
V
V
ns
ns
ns
ns
ns
V
V
V
V
V
mF
°C
°C
DC Electrical Characteristics
Symbol Parameter
Test Conditions
ICC
IEE
IREF
IIL
IIH
COUT
CIN
ROUT
Power Supply Current
Power Supply Current
Reference Input Current
Logic 0 Input Current
Logic 1 Input Current
Output Capacitance
Digital Input Capacitance
Output Resistance
TTL Mode, VCC = Max, VEE = Max
TTL Mode, VCC = Max, VEE = Max1
VEE = Max, VREF = -10V
TTL Mode, VCC = Max, VEE = Max
ECL Mode, VCC = 0.0, VEE = Max
TTL Mode, VCC = Max, VEE = Max
ECL Mode, VCC = 0.0, VEE = Max
AOUT to AGND (Figure 2)
Any Digital Input to DGND
AOUT to AGND (Figure 2)
Note:
1. Return current from VEE flows through AGND.
Temperature Range
Standard Extended
Min. Max. Min. Max. Unit
20 20 mA
-130
-150 mA
10 10 mA
-1.0 -1.0 mA
-300
-300 mA
75 75 mA
350 350 mA
10 10 pF
35 35 pF
70 95 70 95 W
5

5 Page





TDC1016 arduino
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
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24 Lead Sidebrazed Ceramic DIP
Symbol
A
b1
b2
c1
D
E
e
eA
L
Q
S1
S2
Inches
Min. Max.
.120 .175
.014 .023
.040 .065
.008 .015
1.180 1.220
.575 .610
.100 BSC
.600 BSC
.125 .200
.025 .060
.005 —
.005 —
Millimeters
Min. Max.
3.05 4.44
.360 .580
1.02 1.65
.200 .380
29.97 30.99
14.60 15.49
2.54 BSC
15.24 BSC
3.18 5.08
.630 1.52
.13 —
.13 —
Notes
7
2
7
4, 8
7
3
5
TDC1016
Notes:
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
2. The minimum limit for dimension "b2" may be .023(.58mm) for leads
number 1, 12, 13, and 24 only.
3. Dimension "Q" shall be measured from the seating plane to the base
plane.
4. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 24.
5. Applies to all four corners (leads number 1, 12, 13, and 24).
6. "eA" shall be measured at the centerline of the leads.
7. All leads – Increase maximum limit by .003(.08mm) measured at the
center of the flat when lead finish is applied.
8. Twenty-two spaces.
12
E
13
S1
A
Q
b2
D
e
Note 1
1
24
S2
L
b1
eA
c1
11

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