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PDF LAMXO2280E Data sheet ( Hoja de datos )

Número de pieza LAMXO2280E
Descripción (LAMXO Series) LA-MachXO Automotive Family
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo



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No Preview Available ! LAMXO2280E Hoja de datos, Descripción, Manual

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LA-MachXO Automotive Family Data Sheet
DS1003 Version 01.5, November 2007

1 page




LAMXO2280E pdf
Lattice Semiconductor
Architecture
LA-MachXO Automotive Family Data Sheet
Fwiwgwu.rDeat2a-S1h.eTeot4pU.Vcoimew of the LA-MachXO1200 Device1
PIOs Arranged into
sysIO Banks
sysMEM Embedded
Block RAM (EBR)
Programmable
Functional Units
with RAM (PFUs)
Programmable
Functional Units
without RAM (PFFs)
sysCLOCK
PLL
JTAG Port
1. Top view of the LA-MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks.
Figure 2-2. Top View of the LA-MachXO640 Device
PIOs Arranged into
sysIO Banks
Programmable
Function Units
without RAM (PFFs)
Programmable
Function Units
with RAM (PFUs)
JTAG Port
2-2

5 Page





LAMXO2280E arduino
Lattice Semiconductor
Architecture
LA-MachXO Automotive Family Data Sheet
Fwiwgwu.rDeat2a-S8h.ePetr4iUm.caormy Clocks for LA-MachXO1200 and LA-MachXO2280 Devices
Up to 9
4
Up to 6
Primary Clock 0
16:1
Primary Clock 1
16:1
Primary Clock 2
16:1
Primary Clock 3
16:1
Routing Clock PLL
Pads Outputs
Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock
sources come from dual function clock pins and 12 come from internal routing.
Figure 2-9. Secondary Clocks for LA-MachXO Devices
12 4
16:1
16:1
Secondary (Control)
Clocks
16:1
Routing Clock
Pads
16:1
2-8

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