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PDF LM1262 Data sheet ( Hoja de datos )

Número de pieza LM1262
Descripción 200 MHz I2C Compatible RGB Video Amplifier System with OSD and DACs
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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March 2002
LM1262
200 MHz I2C Compatible RGB Video Amplifier System
with OSD and DACs
General Description
The LM1262 pre-amp is an integrated CMOS CRT pre-amp.
The IC is I2C compatible, and allows control of all the pa-
rameters necessary to directly setup and adjust the gain and
contrast in the CRT display. Brightness and bias can be
controlled through the DAC outputs, and is well matched to
the LM2479 and LM2480 integrated bias clamp IC.
The LM1262 pre-amp is designed to work in cooperation
with the LM246X high gain driver family.
Black level clamping of the signal is carried out directly on
the AC coupled input signal into the high impedance pream-
plifier input, thus eliminating the need for additional black
level clamp capacitors.
The IC is packaged in an industry standard 24-lead DIP
molded plastic package.
Features
n I2C compatible interface
n 4 external 8-bit DACs for bus controlled Bias and
Brightness
n Vertical blank from sandcastle or input at pin 13 OR’ed
with horz. blank signal, option selected by I2C
n Contrast and brightness updates synchronous with
vertical blank, enabled by I2C
n Video set to black level through I2C
n Suitable for use with discrete or integrated clamp, with
software configurable Brightness mixer
n Power Save (Green) Mode, 80% power reduction
n Matched to 11-lead LM246X driver
Applications
n High end 19” and 21” bus controlled monitors with OSD
n 1600 X 1200, 85 Hz or higher applications
n Low cost and high performance system with LM246X
driver
Block and Connection Diagram
FIGURE 1. Order Number LM1262NA
See NS Package Number N24D
DS200404-1
© 2002 National Semiconductor Corporation DS200404
www.national.com

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LM1262 pdf
External Interface Signals Electrical Characteristics (Continued)
Unless otherwise noted: TA = 25˚C, VCC = +5V, VIN = 0.7V, VABL = VCC, CL = 5 pF, Video Output = 2VP-P.
Symbol
Parameter
Conditions
Min Typ Max
(Note 7) (Note 6) (Note 7)
tH-Blank on
H-Blank Time Delay from Zero Rising Edge of the Flyback
Crossing Point of H Flyback
Signal
50
tH-Blank off
H-Blank Time Delay from Zero Falling Edge of the Flyback
Crossing Point of H Flyback
Signal
50
IIn Threshold
IIn H-Blank Detection
Threshold
−20
IIn-Operating
Minimum — Insure Normal
Operation
Maximum — Should Not
Exceed in Normal Operation
Lowest Operating Horizontal
Frequency in Given Application
(Note 17)
−30
−300
IIn Flyback
Peak Current during Flyback Operating Range for all
Period, Recommended Design Horizontal Scan Frequencies,
Range
Maximum Current Should Not
0.5
1.5
2.0
Exceed 2 mA (Note 17)
Units
ns
ns
µA
µA
mA
Note 1: Limits of Absolute Maximum Ratings indicate limits below which damage to the device must not occur.
Note 2: Limits of operating ratings indicate required boundaries of conditions for which the device is functional, but may not meet specific performance limits.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
Note 4: Human body model, 100 pF discharged through a 1.5 kresistor.
Note 5: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specified voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50).
Note 6: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: The supply current specified is the quiescent current for VCC with RL = . Load resistors are not required and are not used in the test circuit, therefore all
the supply current is used by the pre-amp.
Note 9: Linearity Error is the variation in step height of a 16 step staircase input signal waveform with 0.7 VP-P level at the input, subdivided into 16 equal steps,
with each step approximately 100 ns in width.
Note 10: Input from signal generator: tr, tf < 1 ns. Scope and generator response used for testing: tr = 1.1 ns, tf = 0.9 ns. Using the RSS technique the scope and
generator response have been removed from the output rise and fall times.
Note 11: AV track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in
gain change between any two amplifiers with the contrast set to AV 1/2 and measured relative to the AV max condition. For example, at AV max the three amplifiers’
gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to AV 1/2. This yields a typical gain change of
10.0 dB with a tracking change of ±0.2 dB.
Note 12: ABL should provide smooth decrease in gain over the operational range of 0 dB to –6 dB
AABL = A(VABL = VABL Max Gain) - A(VABL = VABL Min Gain)
Beyond –6 dB the gain characteristics, linearity, pulse response, and/or behavior may depart from normal values.
Note 13: Adjust input frequency from 10 MHz (AV max reference level) to the −3 dB corner frequency (f−3 dB).
Note 14: Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier
inputs to simulate generator loading. Repeat test at fIN = 10 MHz for Vsep 10 MHz.
Note 15: A minimum pulse width of 200 ns is guaranteed for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used then a longer
clamp pulse may be required.
Note 16: The internal circuit detects the vertical blank only when this signal is present in the sandcastle input. There is typically an 800 nsec delay in detecting the
vertical blank signal. If only the horizontal clamp is present the vertical blank will not be activated. Rise and fall times of the sandcastle input signal should be 10 nsec
or faster.
Note 17: Limits met by matching the external resistor going to pin 24 to the H Flyback voltage.
Note 18: A 4.7 kresistor must be in series with pin 13 when this pin is the input for vertical blanking. When the LM1262 is first turned on the default condition for
pin 13 is for the DAC4 output. Under this condition pin 13 will be damaged by the vertical blanking input if a series resistor is not used.
5 www.national.com

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LM1262 arduino
Functional Description
All functions of the LM1262 are controlled through the I2C
Bus. Details on the internal registers are covered in the
I2C Interface Registers Section. Figure 1 shows the block
diagram of the LM1262. The I2C signals come in on pins
11 and 12 and go to the I2C Interface. Both the internal
blocks with an “R” and the four external DACs are con-
trolled by the I2C Interface. The video and OSD blocks
are shown for the red channel in Figure 1. The blocks for
both the green and blue channels are not shown; how-
ever, they are identical to the red channel.
Proper operation of the LM1262 does require a very
accurate reference voltage. This voltage is generated in
the VRef block. To insure an accurate voltage over tem-
perature, an external resistor is used to set the current in
the VRef stage. The external resistor is connected to pin
10. This resistor should be 1% and have a temperature
coefficient under 100 ppm/˚C. ALL VIDEO SIGNALS
MUST BE KEPT AWAY FROM PIN 10. This pin has a very
high input impedance and will pick up any high frequency
signals routed near it. The board layout shown in Figure
10 is a good example of trace routing near pin 10. The
output of the VRef stage goes to a number of blocks in the
video section and also to pin 21. This pin allows capacitor
filtering on the VRef output and offers an accurate external
reference. A buffer must be used with this reference, the
maximum current loading should be only 100 µA.
Note: Any noise injected into pin 21 will appear on the video. The voltage
reference must be kept very clean for best performance of the
LM1262.
The video inputs are pins 5, 6, and 7. Looking at the red
channel (pin 5) note that the “Clamp DC Restore Amp” is
connected to this pin. Since the video must be AC coupled to
the LM1262, the coupling cap is also used to store the
reference voltage for DC restoration. The “Clamp DC Re-
store Amp” block charges the input capacitor to the correct
voltage when the clamp pulse (pin 23) is active. The “Hi Z
Input Buffer Amp” buffers the video signal for internal pro-
cessing. Input impedance to this stage is typically 20 M.
With such a high impedance the DC restoration can appear
to be working for a number of minutes after the clamp pulse
is removed.
The output of the Buffer Amp goes to the Contrast stage. The
7 bit contrast register (03h) sets the contrast level through
the I2C bus. This register controls the Contrast stage in each
video channel. Contrast adjustment range is up to −20 dB.
Loading all zeros in the contrast register gives −20 dB at-
tenuation. All ones will give no attenuation. The output of this
stage is used as the feedback for the DC restoration loop.
“Auto Beam Limit Amp” or ABL is the next block in the video
path. This is a voltage controlled gain stage which gives no
attenuation with 5V at pin 22 and gives about −10 dB attenu-
ation with 2V at pin 2. ABL is covered in more detail later in
this section.
Next in the video path is the “OSD Mixer”. The OSD Select
signal at pin 4 controls this stage, selecting OSD with a high
at pin 4, and video with a low at pin 4. Since the DC
restoration feedback is at the Contrast output, the video
black level will match the OSD black level. The OSD signal is
mixed with the video signal at the output of this stage.
The OSD goes through the “OSD Contrast” stage before
entering the “OSD Mixer” block. Bits 3 and 4 of register 08h
control the OSD contrast giving four video levels for the OSD
window. Maximum video level for the OSD window occurs
with both bits set to one. Minimum video level will occur with
both bits set to a zero.
Following the “OSD Mixer” is the “Gain” block. Each video
channel has its own independent control of this block so the
user can balance the color of the CRT display. Registers
00h, 01h, 02h are used for the gain attenuation. These
registers are 7 bits with the maximum attenuation of −10 dB
occurring when all zeros are loaded.
The final block in the video path is the “Output Buffer Amp”.
This stage provides the drive needed for the inputs of a CRT
driver. The recommended driver for this pre-amp is one of
the LM246X family. Horizontal blanking is also added to the
video signal from the “H Blank” stage. This block is covered
in more detail below. DC offset of the output is set by the “DC
DACs Offset” stage. Bits 0 through 2 in register 08 control
this stage. This gives 8 different black levels ranging from
0.75V to 1.55V. When using one of the LM246X CRT driver
family it is recommended that the black level be set to 1.25V.
ABL: The Auto Beam Limit control reduces the gain of the
video amplifiers in response to a control voltage proportional
to the CRT beam current. The ABL acts on all three channels
in an identical manner. This is required for CRT life and X-ray
protection. The beam current limit circuit application is as
shown in Figure 4: when no current is being drawn by the
EHT supply, current flows from the supply rail through the
ABL resistor and into the ABL input of the IC. The IC clamps
the input voltage to a low impedance voltage source (the 5V
supply rail).
When current is drawn from the EHT supply, some of the
current passing through the ABL resistor goes to the EHT
supply, which reduces the current flowing into the ABL input
of the IC.
When the EHT current is high enough, the current flowing
into the ABL input of the IC drops to zero. This current level
determines the ABL threshold and is given by:
Where:
VS is the external supply (usually the CRT driver supply rail,
about 80V)
VABL TH is the threshold ABL voltage of the IC
RABL is the ABL resistor value
IABL is the ABL limit
When the voltage on the ABL input drops below the ABL
threshold of the pre-amp, the gain of the pre-amp reduces,
which reduces the beam current. A feedback loop is thus
established which acts to prevent the average beam current
exceeding IABL.
11 www.national.com

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