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PDF M38D2 Data sheet ( Hoja de datos )
| Número de pieza | M38D2 | |
| Descripción | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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38D2 Group
SIwNwGw.LDEat-aCShHeeIPt4U8.c-BomIT CMOS MICROCOMPUTER
REJ03B0177-0302
Rev.3.02
Apr 10, 2008
DESCRIPTION
The 38D2 Group is the 8-bit microcomputer based on the 740
Family core technology.
The 38D2 Group is pin-compatible with the 38C2 Group.
The 38D2 Group has an LCD drive control circuit, an A/D
converter, a serial interface, and a ROM correction function and
on-chip oscillator as additional functions.
The QzROM version and the flash memory version are available.
The flash memory version does not have a selection function for
the oscillation start mode. Only the on-chip oscillator starts
oscillating.
The various microcomputers include variations of memory size,
and packaging. For details, refer to the section on part
numbering.
FEATURES
• Basic machine-language instructions ................................. 71
• The minimum instruction execution time ................... 0.32 μs
(at 12.5 MHz oscillation frequency)
• Memory size (QzROM version)
ROM ........................................................ 16 K to 60 K bytes
RAM ........................................................... 640 to 2048 bytes
• Memory size (Flash memory version)
ROM ...................................................................... 60 K bytes
RAM ...................................................................... 2048 bytes
• Programmable input/output ports .. 51 (common to SEG: 24)
• Interrupts ............................................. 18 sources, 16 vectors
• Timers ..................................................... 8-bit × 4, 16-bit × 2
• Serial interface ....... 8-bit × 2 (UART or Clock-synchronized)
• PWM .......... 10-bit × 2, 16-bit × 1 (common to IGBT output)
• A/D converter .......................................... 10-bit × 8 channels
(A/D converter can be operated in low-speed mode.)
• Watchdog timer ......................................................... 8-bit × 1
• ROM correction function ....................... 32 bytes × 2 vectors
• LED direct drive port ............................................................ 8
(average current: 15 mA, peak current: 30 mA, total current: 90 mA)
• LCD drive control circuit
Bias ............................................................................ 1/2, 1/3
Duty .............................................................................. 2, 3, 4
Common output .................................................................... 4
Segment output ................................................................... 24
• Main clock generating circuit ............................................... 1
(connect to external ceramic resonator or on-chip oscillator)
• Sub-clock generating circuit ..................................................1
(connect to external quartz-crystal oscillator)
• Power source voltage (QzROM version)
[In frequency/2 mode]
f(XIN) ≤ 12.5 MHz.............................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 4.0 to 5.5 V
f(XIN) ≤ 4 MHz................................................... 2.0 to 5.5 V
f(XIN) ≤ 2 MHz................................................... 1.8 to 5.5 V
[In frequency/4 mode]
f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 2.0 to 5.5 V
f(XIN) ≤ 4 MHz................................................... 1.8 to 5.5 V
[In frequency/8 mode]
f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 2.0 to 5.5 V
f(XIN) ≤ 4 MHz................................................... 1.8 to 5.5 V
[In low-speed mode].............................................. 1.8 to 5.5 V
Note. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the fre-
quency/2 mode.
• Power source voltage (Flash memory version)
[In frequency/2 mode]
f(XIN) ≤ 12.5 MHz.............................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 4.0 to 5.5 V
f(XIN) ≤ 4 MHz................................................... 2.7 to 5.5 V
[In frequency/4 mode]
f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 2.7 to 5.5 V
[In frequency/8 mode]
f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V
f(XIN) ≤ 8 MHz................................................... 2.7 to 5.5 V
[In low-speed mode].............................................. 2.7 to 5.5 V
Note. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the fre-
quency/2 mode.
• Power dissipation (QzROM version)
• In frequency/2 mode ..................................... Typ. 32 mW
(VCC = 5 V, f(XIN) = 12.5 MHz, Ta = 25°C)
• In low-speed mode ........................................ Typ. 18 μW
(VCC = 2.5 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25°C)
• Power dissipation (Flash memory version)
• In frequency/2 mode ..................................... Typ. 20 mW
(VCC = 5 V, f(XIN) = 12.5 MHz, Ta = 25°C)
• In low-speed mode ...................................... Typ. 1.1 mW
(VCC = 2.7 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25°C)
• Operating temperature range ............................... −20 to 85°C
Flash Memory Mode
• Program/Erase voltage ............................. VCC = 2.7 to 5.5 V
• Program method ....................... Programming in unit of byte
• Erase method .................................................... Block erasing
• Program/Erase control by software command
APPLICATION
Household products, Consumer electronics, etc.
Rev.3.02 Apr 10, 2008 Page 1 of 131
REJ03B0177-0302
1 page  
38D2 Group
PwINwwD.DEaStaCSRhIePeTt4IUO.Ncom
Table 2 Pin description (1)
Pin
VCC, VSS
RESET
XIN
XOUT
Name
Power source
Reset input
Clock input
Clock output
VL3
COM0−
COM3
LCD power
source
Common output
P00/SEG0/(KW4)−
P03/SEG3/(KW7)
P04/SEG4−
P07/SEG7
I/O port P0
P10/SEG8−
P17/SEG15
I/O port P1
P20/SEG16−
P25/SEG21
P26/SEG22/VL1
P27/SEG23/VL2
I/O port P2
P30/SRDY2/(LED0)
P31/SCLK2/(LED1)
P32/TxD2/(LED2)
P33/RxD2/(LED3)
P34/INT2/(LED4)
P35/TXOUT1/(LED5)
P36/T2OUT/CKOUT/
(LED6)
P37/CNTR0/TXOUT2/
(LED7)
P40/OOUT0/AN0
P41/OOUT1/AN1
I/O port P3
I/O port P4
P42/AN2/ADKEY
P43/AN3−P45/AN5
P46/RTP0/AN6
P47/RTP1/AN7
P50/INT0
P51/INT1
P52/T3OUT/PWM0
P53/T4OUT/PWM1
P54/RxD1/(KW0)
P55/TxD1/(KW1)
P56/SCLK1/(KW2)
P57/SRDY1/(KW3)
I/O port P5
Function
• Apply 1.8 to 5.5 V to VCC, and 0 V to VSS.
• Reset input pin for active “L”.
Function except a port function
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to
set the oscillation frequency. When an external clock is used, connect the clock source to
XIN, and leave XOUT pin open.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.
• Input 0 − VL3 voltage to LCD.
• LCD common output pins.
• COM2 and COM3 are not used at 1/2 duty ratio.
• COM3 is not used at 1/3 duty ratio.
• 8-bit I/O port.
• LCD segment
• CMOS compatible input level.
output pins
• CMOS 3-state output structure.
• I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in a bit unit.
• Key input interrupt
input pins
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in a bit unit.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in a bit unit.
• LCD power source
pins
• 8-bit I/O port.
• Serial I/O2 function pins
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be
individually programmed as either input or output. • External interrupt pin
• Pull-up control is enabled in 4-bit unit.
• Timer X, Timer 2 output pins
• Timer X function pin
• 8-bit I/O port.
• A/D convertor
• CMOS compatible input level.
input pins
• CMOS 3-state output structure.
• I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in 4-bit unit.
• Oscillation
external output
pins
• ADKEY
• Real time port
function pins
• 8-bit I/O port.
• External input pins
• CMOS compatible input level.
• CMOS 3-state output structure.
• Timer 3, Timer 4 output pins
• I/O direction register allows each pin to be
• PWM output pins
individually programmed as either input or output.
• Pull-up control is enabled in 4-bit unit
• Serial I/O1 function pins
• Key input interrupt input pins
Rev.3.02 Apr 10, 2008 Page 5 of 131
REJ03B0177-0302
5 Page 
38D2 Group
FwUwNwC.DTaIOtaSNhAeLet4DUE.cSoCmRIPTION
Central Processing Unit (CPU)
The 38D2 Group uses the standard 740 Family instruction set.
Refer to the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
The central processing unit (CPU) has six registers. Figure 5
shows the 740 Family CPU register structure.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as
arithmetic data transfer, etc., are executed mainly through the
accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y
and specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and
interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0”, the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Table 6 shows the push and pop instructions of accumulator or
processor status register.
Store registers other than those described in Figure 6 with
program when the user needs them during interrupts or
subroutine calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
b15
PCH
b7
A
b0
Accumulator
b7
X
b0
Index register X
b7
Y
b0
Index register Y
b7
S
b0
Stack pointer
b7
PCL
b0
Program counter
b7 b0
N V T B D I Z C Processor status register (PS)
Fig. 5 740 Family CPU register structure
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Rev.3.02 Apr 10, 2008 Page 11 of 131
REJ03B0177-0302
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M38D2.PDF ] | |
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