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NCP1200A
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Controller for Universal
Off−Line Supplies Featuring
Low Standby Power
Housed in SOIC−8 or PDIP−8 package, the NCP1200A enhances
the previous NCP1200 series by offering a reduced optocoupler
current together with an increased drive capability. Due to its novel
concept, the circuit allows the implementation of complete off−line
AC−DC adapters, battery charger or a SMPS where standby power is a
key parameter.
With an internal structure operating at a fixed 40 kHz, 60 kHz or
100 kHz, the controller supplies itself from the high−voltage rail,
avoiding the need of an auxiliary winding. This feature naturally eases
the designer task in battery charger applications. Finally,
current−mode control provides an excellent audio−susceptibility and
inherent pulse−by−pulse control.
When the current setpoint falls below a given value, e.g. the output
power demand diminishes, the IC automatically enters the so−called
skip cycle mode and provides excellent efficiency at light loads.
Because this occurs at a user adjustable low peak current, no acoustic
noise takes place.
The NCP1200A features an efficient protective circuitry which, in
presence of an overcurrent condition, disables the output pulses while
the device enters a safe burst mode, trying to restart. Once the default
has gone, the device auto−recovers.
Features
• Pb−Free Packages are Available
• No Auxiliary Winding Operation
• Auto−Recovery Internal Output Short−Circuit Protection
• Extremely Low No−Load Standby Power
• Current−Mode Control with Skip−Cycle Capability
• Internal Temperature Shutdown
• Internal Leading Edge Blanking
• 250 mA Peak Current Capability
• Internally Fixed Frequency at 40 kHz, 60 kHz and 100 kHz
• Direct Optocoupler Connection
• SPICE Models Available for TRANsient and AC Analysis
• Pin to Pin Compatible with NCP1200
Typical Applications
• AC−DC Adapters for Portable Devices
• Offline Battery Chargers
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
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MINIATURE PWM
CONTROLLER FOR HIGH
POWER AC−DC WALL
ADAPTERS AND OFFLINE
BATTERY CHARGERS
8
1
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS
8
200Ay
ALYW
1
PDIP−8
P SUFFIX
CASE 626
8
1200APxxx
AWL
YYWW
1
xxx = Specific Device Code
(40, 60 or 100)
y = Specific Device Code
(4 for 40, 6 for 60, 1 for 100)
A = Assembly Location
WL, L = Wafer Lot
Y, YY = Year
W, WW = Work Week
PIN CONNECTIONS
Adj 1
FB 2
CS 3
GND 4
8 HV
7 NC
6 VCC
5 Drv
(Top View)
© Semiconductor Components Industries, LLC, 2004
October, 2004− Rev. 5
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
1 Publication Order Number:
NCP1200A/D
VCC
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12 V
10 V
5.4 V
NCP1200A
REGULATION
OCCURS
HERE
LATCHOFF
PHASE
TIME
Drv
INTERNAL
FAULT FLAG
DRIVER
PULSES
DRIVER
PULSES
TIME
STARTUP PHASE
FAULT IS
RELAXED
FAULT OCCURS HERE
TIME
Figure 21. If the fault is relaxed during the VCC natural fall down sequence, the IC automatically resumes.
If the fault still persists when VCC reached UVLOL, then the controller cuts everything off until recovery.
When this level crosses 5.4 V typical, the controller enters
a new startup phase by turning the current source on: VCC
rises toward 12 V and again delivers output pulses at the
UVLOH crossing point. If the fault condition has been
removed before UVLOL approaches, then the IC continues
its normal operation. Otherwise, a new fault cycle takes
place. Figure 21 shows the evolution of the signals in
presence of a fault.
Calculating the VCC Capacitor
As the above section describes, the fall down sequence
depends upon the VCC level: how long does it take for the
VCC line to go from 12 V to 10 V? The required time depends
on the startup sequence of your system, i.e. when you first
apply the power to the IC. The corresponding transient fault
duration due to the output capacitor charging must be less
than the time needed to discharge from 12 V to 10 V,
otherwise the supply will not properly start. The test consists
in either simulating or measuring in the lab how much time
the system takes to reach the regulation at full load. Let’s
suppose that this time corresponds to 6 ms. Therefore a VCC
fall time of 10 ms could be well appropriated in order to not
trigger the overload detection circuitry. If the corresponding
IC consumption, including the MOSFET drive, establishes
at 1.8 mA for instance, we can calculate the required
capacitor using the following formula:
Dt
+
DV @
i
C
, with
DV = 2 V. Then for a wanted Dt of 10 ms, C equals 9 mF or
22 mF for a standard value. When an overload condition
occurs, the IC blocks its internal circuitry and its
consumption drops to 350 mA typical. This happens at
VCC = 10 V and it remains stuck until VCC reaches 5.4 V: we
are in latchoff phase. Again, using the calculated 22 mF and
350 mA current consumption, this latchoff phase lasts:
296 ms.
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