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PDF EM6128K800V Data sheet ( Hoja de datos )
| Número de pieza | EM6128K800V | |
| Descripción | 128Kx8 LP SRAM | |
| Fabricantes | Eorex Corporation | |
| Logotipo |  |
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128Kx8 LP SRAM EM6128K800V Series
GENERAL DESCRIPTION
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The EM6128K800V is a 1,048,576-bit low power CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology.
Its standby current is stable within the range of operating temperature.
The EM6128K800V is well designed for low power application, and particularly well suited for battery
back-up nonvolatile memory application.
The EM6128K800V operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are
fully TTL compatible
FEATURES
z Fast access time: 35/55/70ns
z Low power consumption:
Operating current:
12/10/7mA (TYP.)
Standby current: -L/-LL version
20/1µA (TYP.)
z Single 2.7V ~ 3.6V power supply
z All inputs and outputs TTL compatible
z Fully static operation
z Tri-state output
z Data retention voltage: 1.5V (MIN.)
z Package:
32-pin 450 mil SOP
32-pin 600 mil P-DIP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
36-ball 6mm x 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
A0-A16
DECODER
128Kx8
MEMORY
ARRAY
DQ0-DQ7
I/O DATA
CURCUIT
CE#
WE#
OE#
CE2
CONTROL
CIRCUIT
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A16
Address Inputs
DQ0 – DQ7 Data Inputs/Outputs
CE#, CE2
Enable Input
WE#
Write Enable Input
OE#
Output Enable Input
Vcc Power Supply
Vss Ground
COLUMN I/O
1 DCC-SR-041004-A
1 page  
128Kx8 LP SRAM EM6128K800V Series
CAPACITANCE (TA = 25°C , f = 1.0MHz)
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PARAMETER
Input Capacitance
SYMBOL
CIN
MIN.
-
MAX.
6
Input/Output Capacitance
CI/O -
8
Note : These parameters are guaranteed by device characterization, but not production tested.
UNIT
pF
pF
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
READ CYCLE
PARAMETER
SYM.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
-35
MIN. MAX.
35 -
- 35
- 35
- 25
10 -
5-
- 15
- 15
10 -
-55
MIN. MAX.
55 -
- 55
- 55
- 30
10 -
5-
- 20
- 20
10 -
70
MIN. MAX.
70 -
- 70
- 70
- 35
10 -
5-
- 25
- 25
10 -
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
PARAMETER
SYM.
-35
-55
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
tWC
tAW
tCW
tAS
tWP
twr
tDW
tDH
tOW*
tWHZ*
MIN.
35
30
30
0
25
0
20
0
5
-
MAX.
-
-
-
-
-
-
-
-
-
15
MIN.
55
50
50
0
45
0
25
0
5
-
MAX.
-
-
-
-
-
-
-
-
-
20
*These parameters are guaranteed by device characterization, but not production tested.
70
MIN. MAX.
70 -
60 -
60 -
0-
55 -
0-
30 -
0-
5-
- 25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5 DCC-SR-041004-A
5 Page 
128Kx8 LP SRAM EM6128K800V Series
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
www.DataSheet4U.com
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
11 DCC-SR-041004-A
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet EM6128K800V.PDF ] | |
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