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PDF C505 Data sheet ( Hoja de datos )
| Número de pieza | C505 | |
| Descripción | 8-bit Single-chip Microcontroller | |
| Fabricantes | Infineon Technologies Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de C505 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Data Sheet, Dec. 2000
C505
C505C
C505A
C505CA
8-Bit Single-Chip Microcontroller
Microcontrollers
Never stop thinking.
1 page  
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8-Bit Single-Chip Microcontroller
C500 Family
Advance Information
• Fully compatible to standard 8051 microcontroller
• Superset of the 8051 architecture with 8 datapointers
• Up to 20 MHz operating frequency
– 375 ns instruction cycle time @16 MHz
– 300 ns instruction cycle time @20 MHz (50 % duty cycle)
• On-chip program memory (with optional memory protection)
– C505(C)(A)-2R :
16K byte on-chip ROM
– C505A-4R/C505CA-4R: 32K byte on-chip ROM
– C505A-4E/C505CA-4E: 32K byte on-chip OTP
– alternatively up to 64k byte external program memory
• 256 byte on-chip RAM
• On-chip XRAM
– C505/C505C : 256 byte
– C505A/C505CA : 1K byte
(more features on next page)
C505/C505C/C505A/
C505CA
Oscillator
Watchdog
XRAM
C505/C505C: 256 byte
RAM
Port 0
C505A/C505CA: 1K byte 256 byte
A/D Converter
C505/C505C : 8-bit Timer
C505A/C505CA : 10-bit 0
Timer 2
Timer
C500
Core
8 Datapointers
Port 1
8-bit
USART
Port 2
1
Full-CAN Controller
C505C/C505CA only
Watchdog Timer
Program Memory
Port 3
C505(C)(A)-2R : 16K ROM
C505A-4R/C505CA-4R : 32K ROM Port 4
C505A-4E/C505CA-4E : 32K OTP
I/O
8 analog inputs /
8 digit. I/O
I/O
I/O
I/O (2-bit I/O port)
Figure 1
C505 Functional Units
Data Sheet
1
12.00
5 Page 
C505/C505C/C505A/C505CA
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Table 2
Pin Definitions and Functions (cont’d)
Symbol
RESET
Pin Number I/O
*)
4I
P3.0-P3.7 5, 7-13
I/O
5
7
8
9
10
11
12
13
*) I = Input
O = Output
Function
RESET
A high level on this pin for two machine cycle while the
oscillator is running resets the device. An internal diffused
resistor to VSS permits power-on reset using only an
external capacitor to VDD.
Port 3
is an 8-bit quasi-bidirectional port with internal pull-up
arrangement. Port 3 pins that have 1’s written to them are
pulled high by the internal pull-up transistors and in that
state can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current (IIL, in the DC
characteristics) because of the internal pullup transistors.
The output latch corresponding to a secondary function
must be programmed to a one (1) for that function to operate
(except for TxD and WR). The secondary functions are
assigned to the pins of port 3 as follows:
P3.0 / RxD
Receiver data input (asynch.) or data
input/output (synch.) of serial interface
P3.1 / TxD
Transmitter data output (asynch.) or
clock output (synch.) of serial interface
P3.2 / INT0
External interrupt 0 input / timer 0 gate
control input
P3.3 / INT1
External interrupt 1 input / timer 1 gate
control input
P3.4 / T0
Timer 0 counter input
P3.5 / T1
Timer 1 counter input
P3.6 / WR
WR control output; latches the data
byte from port 0 into the external data
memory
P3.7 / RD
RD control output; enables the external
data memory
Data Sheet
7
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| PDF Descargar | [ Datasheet C505.PDF ] | |
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