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PDF K7J643682M Data sheet ( Hoja de datos )

Número de pieza K7J643682M
Descripción (K7J641882M / K7J643682M) 72Mb M-die DDRII SRAM Specification
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K7J643682M
wKww7.DJata6S4he1et84U8.c2omM
2Mx36 & 4Mx18 DDR II SIO b2 SRAM
72Mb M-die DDRII SRAM Specification
165 FBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 - Aug. 2005
Rev 1.0

1 page




K7J643682M pdf
K7J643682M
wKww7.DJata6S4he1et84U8.c2omM
2Mx36 & 4Mx18 DDR II SIO b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7J641882M(4Mx18)
12345678
A
CQ VSS/SA* SA
R/W
BW1
K
NC LD
B NC Q9 D9 SA NC
K
BW0
SA
C NC NC D10 VSS SA SA SA VSS
D NC D11 Q10 VSS VSS VSS VSS VSS
E NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
K NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
M NC
NC D16 VSS VSS VSS VSS VSS
N NC D17 Q16 VSS SA SA SA VSS
P NC
NC Q17 SA
SA
C
SA SA
R TDO TCK
SA
SA
SA
C
SA SA
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 144Mb.
2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17.
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-17
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,
3F,2G,3J,3L,3M,2N
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
NOTE
1
Q0-17
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,
2F,3G,3K,2L,3N,3P
Data Outputs
R/W
4A
Read, Write Control Pin, Read active
when high
LD
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1
VREF
ZQ
VDD
VDDQ
7B, 5A
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
2
VSS
TMS
TDI
TCK
TDO
NC
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
10R
11R
2R
1R
7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F,
10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M,2M,
9M,1N,9N,10N,1P,2P,9P
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
- 5 - Aug. 2005
Rev 1.0

5 Page





K7J643682M arduino
K7J643682M
wKw7Jw64. 1D8a82t Ma S h e e t 4 U . c o m 2Mx36 & 4Mx18 DDR II SIO b2 SRAM
THERMAL RESISTANCE
PRMETER
Junction to Ambient
Junction to Case
SYMBOL
θJA
θJC
TYP
21
2.48
Unit
°C/W
°C/W
NOTES
Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. TJ=TA + PD x θJA
PIN CAPACITANCE
PRMETER
SYMBOL
Address Control Input Capacitance
CIN
Input and Output Capacitance
COUT
Clock Capacitance
CCLK
Note: 1. Parameters are tested with RQ=250and VDDQ=1.5V.
2. Periodically sampled and not 100% tested.
TESTCONDITION
VIN=0V
VOUT=0V
-
Typ MAX Unit NOTES
3.5 4 pF
4 5 pF
3 4 pF
AC TEST CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High/Low Level
Input Reference Level
Input Rise/Fall Time
Output Timing Reference Level
Sym-
VDD
VDDQ
VIH/
VREF
TR/TF
Value
1.7~1.9
1.4~1.9
1.25/0.25
0.75
0.3/0.3
VDDQ/2
Unit
V
V
V
V
ns
V
AC TEST OUTPUT LOAD
VREF 0.75V
VDDQ/2
SRAM
Zo=50
50
250
ZQ
Note: Parameters are tested with RQ=250
Overershoot Timing
Undershoot Timing
VDDQ+0.5V
VDDQ+0.25V
VDDQ
20% tKHKH(MIN)
VIL
VIH
VSS
VSS-0.25V
VSS-0.5V
Note: For power-up, VIH VDDQ+0.3V and VDD 1.7V and VDDQ 1.4V t 200ms
20% tKHKH(MIN)
- 11 -
Aug. 2005
Rev 1.0

11 Page







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