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PDF LM1236 Data sheet ( Hoja de datos )
| Número de pieza | LM1236 | |
| Descripción | 150 MHz I2C Compatible RGB Preamplifier | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
September 2003
www.DataSheet4U.com
LM1236
150 MHz I2C Compatible RGB Preamplifier with Internal
254 Character OSD ROM, 512 Character RAM and 4
DACs
General Description
The LM1236 pre-amp is an integrated CMOS CRT preamp.
It has an I2C compatible interface which allows control of all
the parameters necessary to directly setup and adjust the
gain and contrast in the CRT display. Brightness and bias
can be controlled through the DAC outputs, which are well
matched to the LM2479 and LM2480 integrated bias clamp
ICs. The LM1236 preamp is also designed to be compatible
with the LM246x high gain driver family.
Black level clamping of the video signal is carried out directly
on the AC coupled input signal into the high impedance
preamplifier input, thus eliminating the need for additional
clamp capacitors. Horizontal and vertical blanking of the
outputs is provided. Vertical blanking is optional and its
duration is register programmable.
The IC is packaged in an industry standard 24-lead DIP
molded plastic package.
Features
n Internal 254 character OSD ROM usable as either (a)
190 2-color plus 64 4-color characters, (b) 318 2-color
characters, or (c) some combination in between
n Internal 512 character RAM, which can be displayed as
one single or two independent windows
n Enhanced I2C compatible microcontroller interface
to allow versatile Page RAM access
n OSD Window Fade In/Fade Out
n OSD Half Tone Transparency
n OSD override allows OSD messages to override video
and the use of burn-in screens with no video output.
n 4 DAC outputs (8-bit resolution) for bus controlled CRT
bias and brightness
n Spot killer which blanks the video outputs when VCC
falls below the specified threshold
n Suitable for use with discrete or integrated clamp, with
software configurable brightness mixer
n 4-Bit Programmable start position for internal
Horizontal Blanking
n Horizontal blanking and OSD synchronization directly
from deflection signals. The blanking can be disabled, if
desired.
n Vertical blanking and OSD synchronization directly from
deflection signals. The blanking width is register
programmable and can be disabled, if desired.
n Power Saving Mode with 65% power reduction
n Matched to LM246x driver and LM2479/80 bias IC’s
Applications
n Low end 15" and 17" bus controlled monitors with OSD
n 1024x768 displays up to 85 Hz requiring OSD capability
n Very low cost systems with LM246x driver
© 2005 National Semiconductor Corporation DS200757
www.national.com
1 page  
DAC Output Electrical Characteristics
Unless otherwise noted: TA = 25˚C, VCC = +5.0V, VIN = 0.7V, VABL = VCC, CL = 8 pF, Video Outputs = 2.0 VP-P. See (Note 7)
for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs.
wSwywm.DbaotlaSheet4U.com Parameter
Conditions
Min Typ Max Units
VMin DAC
VMax DAC
Mode 00
Min Output Voltage of DAC
Max Output Voltage of DAC
Register Value = 0x00
Register Value = 0xFF,
DCF[1:0] = 00b
0.5 0.7
4.2
V
V
VMax DAC
Mode 01
∆VMax DAC
(Temp)
Max Output Voltage of DAC in
DCF Mode 01
DAC Output Voltage Variation
with Temperature
Register Value = 0xFF,
DCF[1:0] = 01b
0 < T < 70˚C ambient
2.35
±0.5
V
mV/˚C
∆VMax DAC (VCC)
Linearity
DAC Output Voltage Variation
with VCC
Linearity of DAC over its Range
VCC varied from 4.75V to 5.25V, DAC
register set to mid-range (0x7F)
50
5
mV
%
Monotonicity
Monotonicity of the DAC
Excluding Dead Zones
±0.5
LSB
IMAX
Max Load Current
1.0 mA
System Interface Signal Characteristics
Unless otherwise noted: TA = 25˚C, VCC = +5.0V, VIN = 0.7V, VABL = VCC, CL = 8 pF, Video Outputs = 2.0 VP-P. See (Note 7)
for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs.
Symbol
Parameter
Conditions
Min Typ Max Units
VVTH+
VFLYBACK Positive Switching
Guarantee
Vertical Blanking triggered
2.0
V
VSPOT
VRef
VIL (SCL, SDA)
VIH (SCL, SDA)
Spot Killer Voltage
VRef Output Voltage (pin 2)
Logic Low Input Voltage
Logic High Input Voltage
Table 14, VCC Adjusted to Activate
IL (SCL, SDA)
IH (SCL, SDA)
VOL (SCL, SDA)
fH Min
fH Max
IHFB IN Max
Logic Low Input Current
Logic High Input Voltage
Logic Low Output Voltage
Minimum Horizontal Frequency
Maximum Horizontal Frequency
Horizontal Flyback Input
SDA or SCL, Input Voltage = 0.4V
SDA or SCL, Input Voltage = 4.5V
IO = 3 mA
PLL & OSD Functioning; PPL = 0
PLL & OSD Functioning; PPL = 4
Current Absolute Maximum during
Flyback
3.4
1.25
−0.5
3.5
3.9
1.45
±10
±10
0.5
25
110
4.3
1.65
1.5
VCC +
0.5
5
V
V
V
V
µA
µA
V
kHz
kHz
mA
IIN
IHFB OUT Max
IOUT
IIN THRESHOLD
tH-BLANK ON
tH-BLANK OFF
VBLANK Max
fFREERUN
Peak Current during Flyback
Design Value
Horizontal Flyback Input Current Absolute Maximum during Scan
Peak Current during Scan
Not exact - Duty Cycle Dependent
IIN H-Blank Detection Threshold
H-Blank Time Delay - On
H-Blank Time Delay - Off
Maximum Video Blanking Level
+ Zero crossing of IHFB to 50% of
output blanking start. I24 = +1.5mA
− Zero crossing of IHFB to 50% of
output blanking end. I24 = −100µA
Test Setting 4, AC input signal
Free Run H Frequency, Including
H Blank
−700
4
−550
0
45
mA
µA
µA
µA
ns
85 ns
0 0.25 V
42 kHz
tPW CLAMP
VCLAMP MAX
Minimum Clamp Pulse Width
Maximum Low Level Clamp
Pulse Voltage
See (Note 15)
Video Clamp Functioning
200 ns
2.0 V
VCLAMP MIN
Minimum High Level Clamp
Pulse Voltage
Video Clamp Functioning
3.0
V
ICLAMP Low
Clamp Gate Low Input Current V23 = 2V
−0.4
µA
5 www.national.com
5 Page 
Pin Descriptions and Application Information (Continued)
Pin
Pin Name
Now. ww.DataSheet4U.com
3 VREF
Schematic
Description
External resistor, 10k 1%, sets the internal bias
current level for optimum performance of the
LM1247. This resistor should be placed as close
to pin 3 and the pin 4 ground return as possible.
4 Analog Input
Ground
5 Blue Video In
6 Red Video In
7 Green Video In
8 Digital Ground
10 Digital VCC
9 PLL Filter
11 SDA
This is the ground for the input analog portions
of the LM1247 internal circuitry.
These video inputs must be AC coupled with a
.0047 µF cap. Internal DC restoration is done at
these inputs. A series resistor of about 33Ω and
external ESD protection diodes should also be
used for protection from ESD damage.
The ground pin should be connected to the rest
of the circuit ground by a short but independent
PCB trace to prevent contamination by
extraneous signals. The VCC pin should be
isolated from the rest of the VCC line by a ferrite
bead and bypassed to pin 8 with an electrolytic
capacitor and a high frequency ceramic.
Recommended topology and values are shown
to the left. It is recommended that both filter
branches be bypassed to the independent
ground as close to pin 8 as possible. Great care
should be taken to prevent external signals from
coupling into this filter from video, I2C, etc.
The I2C compatible data line. A pull-up resistor
of about 2 kΩ should be connected between this
pin and VCC. A resistor of at least 100Ω should
be connected in series with the data line for
additional ESD protection.
11 www.national.com
11 Page | ||
| Páginas | Total 43 Páginas | |
| PDF Descargar | [ Datasheet LM1236.PDF ] | |
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