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PDF 29LV320D Data sheet ( Hoja de datos )

Número de pieza 29LV320D
Descripción AM29LV320D
Fabricantes AMD 
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Am29LV320D
Data Sheet
www.DataSheet4U.com
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Publication Number 23579 Revision C Amendment +3 Issue Date September 19, 2003

1 page




29LV320D pdf
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Cwownwn.DeacttaiSohneeDt4iaUg.croamms . . . . . . . . . . . . . . . . . . . . . . . 5
Special Package Handling Instructions .................................... 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences ............................ 10
Accelerated Program Operation .......................................... 10
Autoselect Functions ........................................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Autoselect Mode ..................................................................... 16
Sector/Sector Block Protection and Unprotection .................. 17
Write Protect (WP#) ................................................................ 18
Temporary Sector Unprotect .................................................. 18
Figure 1. Temporary Sector Unprotect Operation........................... 18
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 19
SecSiTM Sector (Secured Silicon) Flash Memory Region ....... 20
Factory Locked: SecSi Sector Programmed
and Protected at the Factory ............................................... 20
Customer Lockable: SecSi Sector NOT Programmed
or Protected at the Factory .................................................. 20
Figure 3. SecSi Sector Protect Verify.............................................. 21
Hardware Data Protection ...................................................... 21
Low VCC Write Inhibit ......................................................... 21
Write Pulse “Glitch” Protection ............................................ 21
Logical Inhibit ...................................................................... 21
Power-Up Write Inhibit ......................................................... 21
Common Flash Memory Interface (CFI) . . . . . . . 21
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ................................................................ 25
Reset Command ..................................................................... 25
Autoselect Command Sequence ............................................ 25
Enter SecSiTM Sector/Exit SecSi Sector
Command Sequence .............................................................. 25
Byte/Word Program Command Sequence ............................. 26
Unlock Bypass Command Sequence .................................. 26
Figure 4. Program Operation .......................................................... 27
Chip Erase Command Sequence ........................................... 27
Sector Erase Command Sequence ........................................ 27
Erase Suspend/Erase Resume Commands ........................... 28
Figure 5. Erase Operation............................................................... 28
Command Definitions ............................................................. 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 30
DQ7: Data# Polling ................................................................. 30
Figure 6. Data# Polling Algorithm ................................................... 30
RY/BY#: Ready/Busy# ........................................................... 31
DQ6: Toggle Bit I .................................................................... 31
Figure 7. Toggle Bit Algorithm......................................................... 31
DQ2: Toggle Bit II ................................................................... 32
Reading Toggle Bits DQ6/DQ2 ............................................... 32
DQ5: Exceeded Timing Limits ................................................ 32
DQ3: Sector Erase Timer ....................................................... 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 8. Maximum Negative Overshoot Waveform ...................... 34
Figure 9. Maximum Positive Overshoot Waveform........................ 34
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 36
Figure 11. Typical ICC1 vs. Frequency ............................................ 36
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Test Setup.................................................................... 37
Figure 13. Input Waveforms and Measurement Levels ................. 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 14. Read Operation Timings ............................................... 38
Figure 15. Reset Timings ............................................................... 39
Word/Byte Configuration (BYTE#) ............................................. 40
Figure 16. BYTE# Timings for Read Operations............................ 40
Figure 17. BYTE# Timings for Write Operations............................ 40
Erase and Program Operations ................................................. 41
Figure 18. Program Operation Timings.......................................... 42
Figure 19. Chip/Sector Erase Operation Timings .......................... 43
Figure 20. Data# Polling Timings (During Embedded Algorithms). 44
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 45
Figure 22. DQ2 vs. DQ6................................................................. 45
Temporary Sector Unprotect ..................................................... 46
Figure 23. Temporary Sector Unprotect Timing Diagram .............. 46
Figure 24. Accelerated Program Timing Diagram.......................... 46
Figure 25. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 47
Alternate CE# Controlled Erase and Program Operations ........ 48
Figure 26. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 49
Erase And Programming Performance . . . . . . . 50
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 50
TSOP and BGA Package Capacitance . . . . . . . . 50
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51
FBD048—48-ball Fine-Pitch Ball Grid Array (FBGA)
6 x 12 mm package ................................................................... 51
TS 048—48-Pin Standard TSOP ............................................... 52
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53
Revision A (November 1, 2000) .............................................. 53
Revision A+1 (January 23, 2001) ........................................... 53
Revision A+2 (February 1, 2001) ............................................ 53
Revision A+3 (July 2, 2001) .................................................... 53
Revision B (July 12, 2002) ...................................................... 53
Revision B+1 (July 30, 2002) .................................................. 53
Revision C (October 25, 2002) ............................................... 53
Revision C+1 (February 16, 2003) ......................................... 53
Revision C+2 (April 4, 2003) ................................................... 54
Revision C+3 (September 19, 2003) ...................................... 54
September 19, 2003
Am29LV320D
3

5 Page





29LV320D arduino
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
thwewwin.DteartnaSahl eceotm4Um.caomnd register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV320D Device Bus Operations
DQ8–DQ15
Operation
Read
Write
Accelerated Program
Standby
CE# OE# WE# RESET# WP#/ACC
L LH
H
L/H
LHL
H (Note 3)
LHL
H
VCC ±
0.3 V
X
X
VCC ±
0.3 V
VHH
H
Addresses
(Note 2)
AIN
AIN
AIN
DQ0– BYTE#
DQ7
= VIH
DOUT
DOUT
(Note 4) (Note 4)
(Note 4) (Note 4)
X High-Z High-Z
BYTE#
= VIL
DQ8–DQ14
= High-Z,
DQ15 = A-1
High-Z
Output Disable
L HH
H
L/H
X
High-Z High-Z
High-Z
Reset
XXX
L
L/H
X
High-Z High-Z
High-Z
Sector Protect (Note 2) L H L
VID
L/H
SA, A6 = L,
A1 = H, A0 = L
(Note 4)
X
X
Sector Unprotect
(Note 2)
LHL
VID
(Note 3)
SA, A6 = H,
A1 = H, A0 = L
(Note 4)
X
X
Temporary Sector
Unprotect
XXX
VID (Note 3)
AIN
(Note 4) (Note 4)
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
4. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
September 19, 2003
Am29LV320D
9

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