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PDF IDT70V38L Data sheet ( Hoja de datos )
| Número de pieza | IDT70V38L | |
| Descripción | HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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HIGH-SPEED 3.3V
64K x 18 DUAL-PORT
STATIC RAM
IDT70V38L
Features
◆ True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆ High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
◆ Low-power operation
– IDT70V38L
Active: 440mW (typ.)
Standby: 660µW (typ.)
◆ Dual chip enables allow for depth expansion without
external logic
◆ IDT70V38 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
◆ M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆ Busy and Interrupt Flags
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
◆ LVTTL-compatible, single 3.3V (±0.3V) power supply
◆ Available in a 100-pin TQFP
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O 9-17L
I/O 0-8L
BUSYL (1,2)
I/O
Control
I/O
Control
A15L
A0L
Address
Decoder
16
CE0L
CE1L
OEL
R/WL
64Kx18
MEMORY
ARRAY
70V38
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
16
SEML
INT
(2)
L
M/S(1)
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2003 Integrated Device Technology, Inc.
1
Address
Decoder
I/O9-17R
I/O0-8R
BUSYR (1,2)
A15R
A0R
.
CE0R
CE1R
OER
R/WR
SEMR
INTR (2)
4850 drw 01
SEPTEMBER 2003
DSC-4850/3
1 page  
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
wTwew.mDatpaSehereat4Ut.ucorme and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V38L
Symbol
Parameter
Test Conditions
Min. Max. Unit
|ILI| Input Leakage Current(1)
VCC = 3.6V, VIN = 0V to VCC
___ 5 µA
|ILO| Output Leakage Current
CE(2) = VIH, VOUT = 0V to VCC
___ 5 µA
VOL Output Low Voltage
IOL = +4mA
___ 0.4 V
VOH Output High Voltage
IOH = -4mA
2.4 ___ V
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Truth Table I - Chip Enable.
4850 tbl 09
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(5) (VCC = 3.3V ± 0.3V)
70V38L15
Com'l Only
70V38L20
Com'l
& Ind
Symbol
Parameter
Test Condition
Version Typ.(1) Max. Typ.(1) Max. Unit
ICC Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(2)
COM'L L 145 235 135 205 mA
IND L ___ ___ 135 220
ISB1 Standby Current
(Both Ports - TTL Level
Inputs)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX(2)
COM'L L 40 70 35 55 mA
IND L ___ ___ 35 65
ISB2 Standby Current
(One Port - TTL Level
Inputs)
CE"A" = VIL and CE"B" = VIH(4)
Active Port Outputs Disabled,
f=fMAX(2), SEMR = SEML = VIH
COM'L L 100 155 90 140 mA
IND L ___ ___ 90 150
ISB3 Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CEL and CER > VCC - 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3)
SEMR = SEML > VCC - 0.2V
COM'L L 0.2 3.0 0.2 3.0 mA
IND L ___ ___ 0.2 3.0
ISB4 Full Standby Current
(One Port - All CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VCC - 0.2V(4),
SEMR = SEML > VCC - 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V,
Active Port Outputs Disabled , f = fMAX(2)
COM'L L 95 150 90 135 mA
IND L ___ ___ 90 145
NOTES:
4850 tbl 10
1. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 90mA (Typ.)
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels of GND
to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Truth Table I - Chip Enable.
5
5 Page 
IDT70V38L
High-Speed 3.3V 64K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
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tWC
ADDR"A"
MATCH
tWP
R/W"A"
DATAIN "A"
ADDR"B"
tAPS(1)
BUSY"B"
tBAA
tDW
VALID
MATCH
tDH
tBDA
tBDD
tWDD
DATAOUT "B"
tDDD(3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL, refer to Chip Enable Truth Table.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
VALID
4850drw 11
Timing Waveform of Write with BUSY (M/S = VIL)
R/W"A"
BUSY"B"
tWB(3)
tWP
tWH (1)
R/W"B"
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'slave' version.
.
4850 drw 12
11
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| PDF Descargar | [ Datasheet IDT70V38L.PDF ] | |
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