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PDF IDT70V3379S Data sheet ( Hoja de datos )
| Número de pieza | IDT70V3379S | |
| Descripción | HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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www.DataSheet4U.com
HIGH-SPEED 3.3V 32K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V3379S
Features:
x True Dual-Port memory cells which allow simultaneous
access of the same memory location
x High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5/6ns (max)
x Pipelined output mode
x Counter enable and reset features
x Dual chip enables allow for depth expansion without
additional logic
x Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
x Separate byte controls for multiplexed bus and bus
matching compatibility
x LVTTL- compatible, single 3.3V (±150mV) power supply for
core
x LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
x Industrial temperature range (-40°C to +85°C) is
available for selected speeds
x Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)
and 208-pin fine pitch Ball Grid Array, and 256-pin
Ball Grid Array
Functional Block Diagram
UBL
LBL
R/WL
CE0L
CE1L
BB
WW
01
LL
BB
WW
10
RR
UBR
LBR
R/WR
CE0R
CE1R
OEL
I/O0 L - I/O1 7 L
CLKL
A14L
A0L
CNTRSTL
ADSL
CNTENL
Counter/
Address
Reg.
Dout0-8_L
Dout0-8_R
Dout9-17_L Dout9-17_R
32K x 18
MEMORY
ARRAY
Din_L
Din_R
ADDR_L
ADDR_R
Counter/
Address
Reg.
OER
,.
I/O0R - I/O17R
CLKR
A14R
A0R
CNTRSTR
ADSR
CNTENR
4833 tbl 01
©2001 Integrated Device Technology, Inc.
1
APRIL 2001
DSC 4833/8
1 page  
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
www.DLeafttaPSohrteet4U.comRight Port
Names
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
Chip Enables
Read/Write Enable
OEL OER Output Enable
A0L - A14L
A0R - A14R
Address
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
CLKL CLKR Clock
ADSL ADSR Address Strobe Enable
CNTENL
CNTENR
Counter Enable
CNTRSTL
UBL - LBL
VDDQL
OPTL
CNTRSTR
UBR - LBR
VDDQR
OPTR
VDD
VSS
Counter Reset
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V)(1)
Option for selecting VDDQX(1,2)
Power (3.3V)(1)
Ground (0V)
4833 tbl 01
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
Truth Table IRead/Write and Enable Control(1,2,3)
Upper Byte Lower Byte
OE CLK CE0 CE1 UB
LB R/W
I/O9-1 8
I/O0-8
MODE
X ↑ L H H H X High-Z High-Z All Bytes Deselected
X ↑ L H H L L High-Z
DIN Write to Lower Byte Only
X ↑ L H L H L DIN High-Z Write to Upper Byte Only
X↑LHLL L
DIN
DIN Write to Both Bytes
L↑L
HHL
H High-Z
DOUT Read Lower Byte Only
L ↑ L H L H H DOUT High-Z Read Upper Byte Only
L ↑ L H L L H DOUT
DOUT Read Both Bytes
H
↑
L
H
L
L
X
High-Z
High-Z Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = VIH.
3. OE is an asynchronous input signal.
4833 tbl 02
6.452
5 Page 
IDT70V3379S
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation(2)
www.DataSheet4U.com
tCH2
tCYC2
tCL2
CLK
CE0
CE1
UB, LB(0-3)
tSC tHC
tSB tHB
tSB tHB
(5)
tSC tHC
(3)
R/W
ADDRESS(4)
tSW tHW
tSA tHA
An
An + 1
An + 2
An + 3
DATAOUT
(1 Latency)
tCKLZ (1)
tCD2
tDC
Qn
Qn + 1
tOHZ
tOLZ
Qn + 2 (5)
(1)
OE
tOE
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
4833 drw 06
2. ADS = VIL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB or LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
Timing Waveform of a Multi-Device Pipelined Read(1,2)
tCYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS(B1)
A0
A1
A2
A3
A4
A5
A6
CE0(B1)
tSC tHC
tSC tHC
DATAOUT(B1)
ADDRESS(B2)
tSA tHA
A0
tCD2
A1
tCD2
Q0
tDC
A2
tCKHZ
Q1
tDC
A3
tCD2
tCKLZ
A4
Q3
tCKHZ
A5
A6
CE0(B2)
tSC tHC
tSC tHC
tCD2
tCKHZ
DATAOUT(B2)
tCKLZ
Q2
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3379 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
6.1412
tCD2
tCKLZ
Q4
4833 drw 07
11 Page | ||
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| PDF Descargar | [ Datasheet IDT70V3379S.PDF ] | |
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