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PDF IDT70V3319 Data sheet ( Hoja de datos )

Número de pieza IDT70V3319
Descripción (IDT70V3319 / IDT70V3399S) HIGH-SPEED 3.3V 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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HIGH-SPEED 3.3V
256/128K x 18
SYNCHRONOUS
IDT70V3319/99S
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
– Due to limited pin count PL/FT option is not supported
on the 128-pin TQFP package. Device is pipelined
outputs only on each port.
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (6Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
Functional Block Diagram
UBL
LBL
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, single 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 128-pin Thin Quad Flatpack, 208-pin fine
pitch Ball Grid Array, and 256-pin Ball
Grid Array
Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
UBR
LBR
FT/PIPEL
R/WL
CE0L
CE1L
OEL
0a 1a 0b 1b
1/0
ab
1
0
1/0
BB
WW
01
LL
Dout0-8_L
Dout9-17_L
BB
WW
10
RR
Dout0-8_R
Do ut9-17_R
1b 0b
b
1a 0a
a
1/0
1
0
1/0
FT/PIPER
R/WR
CE0R
CE1R
OER
FT/PIPEL
1b 0b 1a 0a
0/1
ab
I/O0L - I/O17L
CLKL
A17 L(1)
A0L
REPEATL
ADSL
CNTENL
NOTE:
1. A17 is a NC for IDT70V3399.
Counter/
Address
Reg.
TDI
TDO
©2003 Integrated Device Technology, Inc.
256K x 18
MEMORY
ARRAY
Din_L
Din_R
ADDR_L
ADDR_R
JTAG
1
0a 1a 0b 1b
ba
0/1
FT/PIPER
Counter/
Address
Reg.
TCK
TMS
TRST
I/O0R - I/O17R
CLKR
A17R(1)
A0R
REPEATR
ADSR
CNTENR
,
5623 tbl 01
MAY 2003
DSC 5623/7
,

1 page




IDT70V3319 pdf
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
www.DLaefttaPSohret et4U.comRight Port
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
OEL
A0L - A17L(1)
OER
A0R - A17R(1)
I/O0L - I/O17L
I/O0R - I/O17R
CLKL
PIPE/FTL(5)
CLKR
PIPE/FTR(5)
ADSL
ADSR
CNTENL
CNTENR
REPEATL
REPEATR
UBL UBR
LBL
VDDQL
LBR
VDDQR
OPTL
OPTR
VDD
VSS
TDI
TDO
TCK
TMS
TRST
Names
Chip Enables(6)
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Pipeline/Flow-Through
Address Strobe Enable
Counter Enable
Counter Repeat(4)
Upper Byte Enable (I/O9-I/O17)(6)
Lower Byte Enable (I/O0-I/O8)(6)
Power (I/O Bus) (3.3V or 2.5V)(2)
Option for selecting VDDQX(2,3)
Power (3.3V)(2)
Ground (0V)
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5623 tbl 01
NOTES:
1. A17 is a NC for IDT70V3399.
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
4. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
5. PIPE/FT option in PK-128 package is not supported due to limitation in pin count.
Device is pipelined output mode only on each port.
6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
65.42

5 Page





IDT70V3319 arduino
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
w(wRwe.DaatadShaeent4Ud.coWm rite Cycle Timing)(2,3) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V3319/99S166
Com'l Only
70V3319/99S133
Com'l
& Ind
Symbol
Parameter
Min. Max. Min. Max. Unit
tCYC1
Clock Cycle Time (Flow-Through)(1)
20 ____ 25 ____ ns
tCYC2
Clock Cycle Time (Pipelined)(1)
6 ____ 7.5 ____ ns
tCH1 Clock High Time (Flow-Through)(1)
6 ____ 7 ____ ns
tCL1 Clock Low Time (Flow-Through)(1)
6 ____ 7 ____ ns
tCH2 Clock High Time (Pipelined)(2)
2.1 ____ 2.6 ____ ns
tCL2 Clock Low Time (Pipelined)(1)
2.1 ____ 2.6 ____ ns
tSA Address Setup Time
1.7 ____ 1.8 ____ ns
tHA Address Hold Time
0.5 ____ 0.5 ____ ns
tSC Chip Enable Setup Time
1.7 ____ 1.8 ____ ns
tHC Chip Enable Hold Time
0.5 ____ 0.5 ____ ns
tSB Byte Enable Setup Time
1.7 ____ 1.8 ____ ns
tHB Byte Enable Hold Time
0.5 ____ 0.5 ____ ns
tSW R/W Setup Time
1.7 ____ 1.8 ____ ns
tHW R/W Hold Time
0.5 ____ 0.5 ____ ns
tSD Input Data Setup Time
1.7 ____ 1.8 ____ ns
tHD Input Data Hold Time
0.5 ____ 0.5 ____ ns
tSAD ADS Setup Time
1.7 ____ 1.8 ____ ns
tHAD ADS Hold Time
0.5 ____ 0.5 ____ ns
tSCN CNTEN Setup Time
1.7 ____ 1.8 ____ ns
tHCN CNTEN Hold Time
0.5 ____ 0.5 ____ ns
tSRPT
REPEAT Setup Time
1.7 ____ 1.8 ____ ns
tHRPT
REPEAT Hold Time
0.5 ____ 0.5 ____ ns
tOE Output Enable to Data Valid
____ 4.0 ____ 4.2 ns
tOLZ Output Enable to Output Low-Z
1 ____
1 ____ ns
tOHZ Output Enable to Output High-Z
1 3.6 1 4.2 ns
tCD1 Clock to Data Valid (Flow-Through)(1)
____ 12 ____ 15 ns
tCD2 Clock to Data Valid (Pipelined)(1)
____ 3.6 ____ 4.2 ns
tDC Data Output Hold After Clock High
1 ____
1 ____ ns
tCKHZ
Clock High to Output High-Z
13
1 3 ns
tCKLZ Clock High to Output Low-Z
1 ____
1 ____ ns
Port-to-Port Delay
tCO Clock-to-Clock Offset
5 ____ 6 ____ ns
NOTES:
5623 tbl 11
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
61.142

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