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PDF 48LC16M16A2 Data sheet ( Hoja de datos )

Número de pieza 48LC16M16A2
Descripción MT48LC16M16A2
Fabricantes Micron Technology 
Logotipo Micron Technology Logotipo

48LC16M16A2 image


1. 256Mbit, SDR SDRAM - Micron






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Synchronous DRAM
MT48LC64M4A2 – 16 Meg x 4 x 4 banks
MT48LC32M8A2 – 8 Meg x 8 x 4 banks
MT48LC16M16A2 – 4 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com
256Mb: x4, x8, x16 SDRAM
Features
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
and auto refresh modes
• Self refresh mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
Table 1: Address Table
Parameter 64 Meg x 4 32 Meg x 8 16 Meg x 16
Configuration
Refresh count
Row
addressing
Bank
addressing
Column
addressing
16 Meg x 4
x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
2K (A0–A9,
A11)
8 Meg x 8
x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
1K (A0–A9)
4 Meg x 16
x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
512 (A0–A8)
Table 2:
Key Timing Parameters
CL = CAS (READ) latency
Speed
Grade
-6A
-7E
-75
-7E
-75
Access Time
Clock
Frequency CL = 2 CL = 3
167 MHz
143 MHz
133 MHz
133 MHz
100 MHz
5.4ns
6ns
5.4ns
5.4ns
5.4ns
Setup
Time
1.5ns
1.5ns
1.5ns
1.5ns
1.5ns
Hold
Time
0.8ns
0.8ns
0.8ns
0.8ns
0.8ns
Part Number Example:
MT48LC16M16A2TG-75:D
Options
Marking
• Configurations
64 Meg x 4 (16 Meg x 4 x 4 banks)
64M4
32 Meg x 8 (8 Meg x 8 x 4 banks)
32M8
16 Meg x 16 (4 Meg x 16 x 4 banks)
• Write recovery (tWR)
tWR = “2 CLK”1
• Plastic package – OCPL2
54-pin TSOP II OCPL2 (400 mil)
16M16
A2
TG
(standard)
54-pin TSOP II OCPL2 (400 mil)
P
Pb-free
60-ball FBGA (x4, x8) (8mm x 16mm)
FB
60-ball FBGA (x4, x8) Pb-free
BB
(8mm x 16mm)
54-ball VFBGA (x16) (8mm x 14 mm)
FG
54-ball VFBGA (x16) Pb-free
BG
(8mm x 14 mm)
• Timing (cycle time)
6.0ns @ CL = 3 (x8, x16 only)
-6A
7.5ns @ CL = 3 (PC133)
-75
7.5ns @ CL = 2 (PC133)
-7E
• Self refresh
Standard
Low power
None
L3
• Operating temperature range
Commercial (0°C to +70°C)
None
Industrial (–40°C to +85°C)
IT
• Design revision
:D
Notes: 1. Refer to Micron technical note: TN-48-05.
2. Off-center parting line.
3. Contact Micron for availability.
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_1.fm - Rev. L 10/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

1 page




48LC16M16A2 pdf
256Mb: x4, x8, x16 SDRAM
List of Tables
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List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
256Mb SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
54-Pin TSOP Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
54-Ball and 60-Ball FBGA Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Truth Table 1 – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Truth Table 3 – Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Truth Table 4 – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
IDD Specifications and Conditions (-6A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
IDD Specifications and Conditions (-7E, -75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Electrical Characteristics and Recommended AC Operating Conditions (-6A) . . . . . . . . . . . . . . . . . .51
Electrical Characteristics and Recommended AC Operating Conditions (-7E, -75) . . . . . . . . . . . . . .52
AC Functional Characteristics (-6A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
AC Functional Characteristics (-7E, -75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAMLOT.fm - Rev. L 10/07 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.

5 Page





48LC16M16A2 arduino
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Figure 5: 60-Ball FBGA Assignment (Top View)
64 Meg x 4 SDRAM
8mm x 16mm “FB”
12
34
56
78
A NC Vss
B NC VssQ
C VDDQ DQ3
D NC NC
E NC VssQ
F VDDQ DQ2
G NC NC
H NC Vss
J NC DQM
K NC CK
L A12 CKE
M A11 A9
N A8 A7
P A6 A5
R A4 Vss
VDD NC
VDDQ
NC
DQ0 VssQ
NC NC
VDDQ
NC
DQ1 VssQ
NC NC
VDD NC
WE# CAS#
RAS# NC
NC CS#
BA1 BA0
A0 A10
A2 A1
VDD A3
256Mb: x4, x8, x16 SDRAM
Pin/Ball Assignments and Descriptions
32 Meg x 8 SDRAM
8mm x 16mm “FB”
12
34
56
78
A DQ7 Vss
B NC VssQ
C VDDQ DQ6
D DQ5 NC
E NC VssQ
F VDDQ DQ4
G NC NC
H NC Vss
J NC DQM
K NC CK
L A12 CKE
M A11 A9
N A8 A7
P A6 A5
R A4 Vss
VDD DQ0
VDDQ
NC
DQ1 VssQ
NC DQ2
VDDQ
NC
DQ3 VssQ
NC NC
VDD NC
WE# CAS#
RAS# NC
NC CS#
BA1 BA0
A0 A10
A2 A1
VDD A3
Depopulated Balls
Depopulated Balls
Note: FBGA pin symbol, type, and descriptions are identical to the listing in Table 4 on page 13.
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM_2.fm - Rev. L 10/07 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.

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