DataSheet.es    


PDF GS88436B Data sheet ( Hoja de datos )

Número de pieza GS88436B
Descripción S/DCD Sync Burst SRAMs
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



Hay una vista previa y un enlace de descarga de GS88436B (archivo pdf) en la parte inferior de esta página.


Total 25 Páginas

No Preview Available ! GS88436B Hoja de datos, Descripción, Manual

Preliminary
GS88418/36B-200/180/166/150/133
1w1w9w-.DBautamShpeet4BUG.coAm
Commercial Temp
Industrial Temp
512K x 18, 256K x 36
200 MHz–133 MHz
8Mb S/DCD Sync Burst SRAMs
3.3 V VDD
3.3 V and 2.5 V I/O
Features
• FT pin for user-configurable flow through or pipelined
operation
• Single/Dual Cycle Deselect Selectable
• ZQ mode pin for user-selectable high/low output drive strength
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 119-bump BGA package
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tCycle
tKQ
IDD
tKQ
tCycle
IDD
-200 -180 -166 -150 -133 Unit
5.0 5. 5 6.0 6.7 7.5 ns
3.0 3.2 3.5 3.8 4.0 ns
450 410 380 350 340 mA
7.5 8 8.5 9.0 9.5 ns
10 10 10 10 10 ns
270 270 250 240 220 mA
Functional Description
Applications
The GS88418/36B is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, in x18 version, E1 and
E2 in x36 version), address burst control inputs (ADSP,
ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered
clock input (CK). Output enable (G) and power-down control
(ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order
(LBO) input. The Burst function need not be used. New
addresses can be loaded on every cycle with no degradation of
chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode bump (Bump 5R). Holding the FT
mode pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS88436B is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the
SCD mode input on Bump 4L.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS884B operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output
power (VDDQ) pins are used to decouple output noise from the
internal circuit.
Rev: 1.05 10/2001
1/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1 page




GS88436B pdf
www.DataSheet4U.com
GS88418/36 Block Diagram
A0–An
Register
DQ
A0
A1
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
D0 Q0
D1 Q1
Counter
Load
A0
A1
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
E1 D Q
FT
G
Power Down
ZZ
Control
Note: Only x18 version shown for simplicity.
Register
DQ
DCD=0
SCD=1
Preliminary
GS88418/36B-200/180/166/150/133
A
Memory
Array
QD
18
4
18
DQx0–DQx9
Rev: 1.05 10/2001 5/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

5 Page





GS88436B arduino
Preliminary
GS88418/36B-200/180/166/150/133
www.DataSheet4U.com
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
VDDQ
VCK
VI/O
VIN
IIN
IOUT
PD
TSTG
TBIAS
Voltage on VDD Pins
Voltage in VDDQ Pins
Voltage on Clock Input Pin
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
Temperature Under Bias
–0.5 to 4.6
–0.5 to VDD
–0.5 to 6
–0.5 to VDDQ +0.5 (4.6 V max.)
–0.5 to VDD +0.5 (4.6 V max.)
+/–20
+/–20
1.5
–55 to 125
–55 to 125
V
V
V
V
V
mA
mA
W
oC
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.
Recommended Operating Conditions
Parameter
Symbol Min. Typ. Max. Unit Notes
Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
VDD
VDDQ
VIH
VIL
TA
TA
3.135
2.375
1.7
–0.3
0
–40
3.3 3.6
V
2.5 VDD
— VDD +0.3
V
V
— 0.8 V
25 70 °C
25 85 °C
1
2
2
3
3
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V VDDQ 2.375 V
(i.e., 2.5 V I/O) and 3.6 V VDDQ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.
Rev: 1.05 10/2001
11/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

11 Page







PáginasTotal 25 Páginas
PDF Descargar[ Datasheet GS88436B.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
GS88436BS/DCD Sync Burst SRAMsGSI Technology
GSI Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar