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PDF TFA9812 Data sheet ( Hoja de datos )
| Número de pieza | TFA9812 | |
| Descripción | BTL stereo Class-D audio amplifier | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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TFA9812
BTL stereo Class-D audio amplifier with I2S input
Rev. 01 — 30 October 2008
Preliminary data sheet
1. General description
The TFA9812 is a high-efficiency Bridge Tied Load (BTL) stereo Class-D audio amplifier
with a digital I2S audio input. It is available in a HVQFN48 package with exposed die
paddle. The exposed die paddle technology enhances the thermal and electrical
performances of the device.
The TFA9812 features digital sound processing and audio power amplification. It supports
I2C control mode and Legacy mode. In Legacy mode I2C involvement is not needed
because the key features are controlled by hardware pin connections.
A continuous time output power of 2 × 12 W (RL = 8 Ω, VDDP = 15 V) is supported without
an external heat sink. Due to the implementation of a programmable thermal foldback
even for high supply voltages, higher ambient temperatures, and/or lower load
impedances, the device operates without sound interrupting behavior.
TFA9812 is designed in such a way that it starts up easily (no special power-up sequence
required). It features various soft and hard impact protection mechanisms to ensure an
application that is both user friendly and robust.
A modulation technique is applied for the TFA9812, which supports common mode choke
approach (1 common mode choke only per BTL amplifier stage). This minimizes the
number of external components.
2. Features
2.1 General features
I 3.3 V and 8 V to 20 V external power supply
I High efficiency and low power dissipation
I Speaker outputs fully short circuit proof across load, to supply lines and ground
I Pop noise free at power-up/power-down and sample rate switching
I Low power sleep mode
I Overvoltage and undervoltage protection on the 8 V to 20 V power supply
I Undervoltage protection on the 3.3 V power supply
I Overcurrent protection (no audible interruptions)
I Overdissipation protection
I Thermally protected and programmable thermal foldback
I Clock error protection
I I2C mode control or Legacy mode (i.e. no I2C) control
I Four different I2C addresses supported
I Internal Phase-Locked Loop (PLL) without using external components
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6. Block diagram
TEST1 TEST2
7 43
AVOL
32
VDDD(3V3) VDDA(3V3) VDDA
40 3 6
PHASED
LOCKED
LOOP
XTALIN 1
XTALOUT 2 OSCILLATOR
MCLK 47
REGISTER
ADDRESS
HEX 01
ADC
TFA9812
CLOCK
PROTECTION
LP
UFP
OFP
IBP
10
CSEL
THERMAL
FOLDBACK
BCK 46
WS 45 SERIAL
AUDIO
DATA 44 INTERFACE
10-BAND
PARAMETRIC
EQUALIZER
VOLUME
CONTROL
AND SOFT
MUTE
INTER-
POLATION
FILTER AND
DE-EMPHASIS
GAIN
POWER
LIMITER
POWERUP 31
ENABLE 33
GAIN 34
CSEL 35
ADSEL2/PLIM2 36
ADSEL1/PLIM1 37
SCL/SFOR 38
SDA/MS 39
CONTROL
INTERFACE
PROTECTION
OVP
UVP
OCP
OTP
ODP
WP
REFERENCES
29
DIAG
30 41 42 4
5
CDELAY STABD REFD STABA REFA
Fig 1. TFA9812 block diagram
PWM
CONTROLLER
CONTROL
LOGIC
CONTROL
LOGIC
DRIVER
HIGH
DRIVER
LOW
STAB1
DRIVER
HIGH
DRIVER
LOW
PWM
CONTROLLER
CONTROL
LOGIC
DRIVER
HIGH
DRIVER
LOW
STAB2
CONTROL
LOGIC
DRIVER
HIGH
DRIVER
LOW
8 48
EXPOSED DIE PADDLE VSS1 VSS2
15 BOOT1P
18, 19 VDDP
16, 17 OUT1P
10, 11 VSSP2
25 BOOT1N
VDDP
23, 24 OUT1N
26, 27 VSSP1
28 STAB1
22 BOOT2P
VDDP
20, 21 OUT2P
VSSP2
12 BOOT2N
VDDP
13, 14 OUT2N
VSSP2
9 STAB2
010aaa217
5 Page 
NXP Semiconductors
www.DataSheet4U.com
TFA9812
BTL stereo Class-D audio amplifier with I2S input
Table 6. I2S master/slave mode selection
Pin value
Clock mode
CSEL SDA/MS
00
legacy
01
legacy
1-
I2C
I2S mode
slave
master
slave or master[1]
[1] Under these conditions the mode is enabled by the appropriate I2C setting.
In I2S slave mode selection between BCK and MCLK clock modes is automatic.
MCLK clock mode is given higher priority than BCK. If the MCLK clock is judged valid by
the protection circuit then MCLK clock mode is enabled. BCK clock mode is enabled when
the MCLK clock is invalid (e.g. not available) and the BCK clock is judged valid by the
protection circuit (see Section 8.7.11).
Table 7 shows the supported crystal frequencies in I2S master mode.
Table 8 shows the supported MCLK frequencies in MCLK mode (I2S slave mode).
Table 9 shows the supported BCK frequencies in BCK mode (I2S slave mode).
Table 7. Valid crystal frequencies in I2S master mode
Control mode
I2C
fs (kHz)
8, 16, 32, 64, 128
11.025, 22.05, 44.1, 88.2,
176.4
12, 24, 48, 96, 192
Legacy
32
44.1
48
Crystal frequency (MHz)
8.192
11.2896
12.288
8.192
11.2896
12.288
Table 8. Valid MCLK frequencies in I2S slave mode
Control mode
I2C
fs (kHz)
8, 16, 32, 64, 128
32
11.025, 22.05, 44.1, 88.2,
176.4
44.1
12, 24, 48, 96, 192
48
MLCK frequency (MHz)
8.192
12.288
18.432 (576 fs)
11.2896
16.9344
25.4016 (576 fs)
12.288
18.432
27.648 (576 fs)
TFA9812_1
Preliminary data sheet
Rev. 01 — 30 October 2008
© NXP B.V. 2008. All rights reserved.
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