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PDF SAF7115 Data sheet ( Hoja de datos )

Número de pieza SAF7115
Descripción Multistandard video decoder
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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SAF7115
Multistandard video decoder with super-adaptive comb filter,
scaler and VBI data read-back via I2C-bus
Rev. 01 — 15 October 2008
Product data sheet
1. General description
The SAF7115 is a video capture device that, due to its improved comb filter performance
and 10-bit video output capabilities, is suitable for various applications such as In-car
video reception, In-car entertainment or In-car navigation.
The SAF7115 is a combination of a two channel analog preprocessing circuit and a high
performance scaler.
The two channel analog preprocessing circuit includes source-selection, an anti-aliasing
filter and Analog-to-Digital Converter (ADC) per channel, an automatic clamp and gain
control, two Clock Generation Circuits (CGC1 and CGC2) and a digital multi standard
decoder that contains two-dimensional chrominance/luminance separation utilizing an
improved adaptive comb filter.
The high performance scaler has variable horizontal and vertical up and down scaling and
a brightness/contrast/saturation control circuit.
The decoder is based on the principle of line-locked clock decoding and is able to decode
the color of PAL, SECAM and NTSC signals into ITU-601 compatible color component
values. The SAF7115 accepts CVBS or S-video (Y/C) from TV or VCR sources as analog
inputs, including weak and distorted signals.
The expansion port (X-port) for digital video (bi-directional half duplex, D1 compatible) can
be used to either output unscaled video using 10-bit or 8-bit dithered resolution or to
connect to other external digital video sources for reuse of the SAF7115 scaler features.
The enhanced image port (I-port) of the SAF7115 supports 8-bit and 16-bit wide output
data with auxiliary reference data for interfacing, e.g. with VGA controller applications. It is
also possible to output video in square pixel formats accompanied by a square pixel clock
of the appropriate frequency.
The SAF7115 also incorporates provisions for capturing the serially coded data in the
Vertical Blanking Interval (VBI-data) of several standards in parallel. Three basic options
are available to transfer the VBI data to other devices:
Capturing raw video samples, after interpolation to the required output data rate,
using the scaler and transferring the data to a device connected to the I-port
Slicing the VBI data using the built-in VBI data slicer (data recovery unit) and
transferring the data to a device connected to the I-port
Slicing the VBI data using the built-in VBI data slicer and reading out the sliced data
through the I2C-bus (for several slow VBI data type standards only)

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SAF7115 pdf
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LLC2 RTS0
LLC RTC0 RTS1
XDQ
XCLK XPD[7:0]
XRH XRDY
XRV XTRI
HPD[7:0]
SDA
SCL
TEST[9:0]
AGND
AI11
AI12
AI21
AI22
AI23
AI24
AOUT
AI1D
AI2D
RESO_N
CE
XTOUT
XTALI
XTALO
RT OUT
EXPANSION PORT PIN MAPPING
I/O CONTROL
I2C-BUS
X PORT I/O FORMATTING
SAF7115
ANALOG
DUAL
ADC
DIGITAL
DECODER
WITH
ADAPTIVE
COMB
FILTER
FIR PREFILTER
PRESCALER
AND
SCALER BCS
LINE
FIFO
BUFFER
VERTICAL
SCALING
HORIZONTAL
FINE
(PHASE)
SCALING
GENERAL
PURPOSE
VBI DATA
SLICER
EVENT CONTROLLER
PULSE GENERATOR
VIDEO/TEXT
ARBITER
VIDEO
FIFO
32
TO
8(16)
MUX
TEXT
FIFO
PLL2
CGC2
FRAME LOCKED
AUDIO CLOCK
PLL
AUDIO CLOCK
GENERATION
PROGRAMMING
REGISTER
ARRAY
A/B
REGISTER
MUX
BOUNDARY
SCAN
TEST
IPD[7:0]
IDQ
IGPH
IGPV
IGP0
IGP1
ICLK
ITRDY
ITRI
VDDA(XTAL)
AXMCLK
ALRCLK
VDDD(CORE) VDDD(IO)
VSSA(XTAL)
ASCLK
AMCLK
VDDA0
VDDA2
VSSD(IO)
VDDA1
VSSD(CORE)
VSSA
TRST_N TMS TDO
TCK
TDI 001aag268
Fig 1. Block diagram

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SAF7115 arduino
NXP Semiconductors
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SAF7115
Multistandard video decoder
Table 4.
Symbol
IGP0
Pin description …continued
Pin
HTQFP100 TFBGA160
48 P12
Type[1]
O
IGPH
53
N14 O
IGPV
52
P13 O
IPD7
IPD6
IPD5
IPD4
IPD3
IPD2
IPD1
IPD0
ITRDY
ITRI
54
55
56
57
59
60
61
62
42
47
M13 O
M14 O
L13 O
L14 O
K14 O
J13 O
J14 O
H13 O
P9 I/pu
N12 I (/O)/pd
Expansion port (X-port)
XCLK
94
XDQ
95
XPD7
81
A5
B4
B11
I/O
I/O
I/O
XPD6
82
A11 I/O
XPD5
84
A10 I/O
XPD4
85
B9
I/O
XPD3
86
A9
I/O
XPD2
87
B8
I/O
XPD1
89
B7
I/O
XPD0
90
A7
I/O
Description
general purpose output signal 0; image port (controlled by
subaddresses 84h and 85h)
multipurpose horizontal reference output signal; image port
(controlled by subaddresses 84h and 85h)
multipurpose vertical reference output signal; image port
(controlled by subaddresses 84h and 85h)
MSB of image port data output
MSB 1 of image port data output
MSB 2 of image port data output
MSB 3 of image port data output
MSB 4 of image port data output
MSB 5 of image port data output
MSB 6 of image port data output
LSB of image port data output
target ready input, image port (with internal pull-up)
image port output control signal, affects all I-port pins including
ICLK, enable and active polarity is under software control (bits
IPE in subaddress 87h) output path used for testing: scan output
clock I/O expansion port
data qualifier I/O expansion port
MSB of expansion-port data: in 8-bit video output mode: this
signal represents the video bit 7; in 10-bit video output mode: this
signal represents the video bit 9
MSB 1 of expansion-port data: in 8-bit video output mode: this
signal represents the video bit 6; in 10-bit video output mode: this
signal represents the video bit 8
MSB 2 of expansion-port data: in 8-bit video output mode: this
signal represents the video bit 5; in 10-bit video output mode: this
signal represents the video bit 7
MSB 3 of expansion-port data: in 8-bit video output mode: this
signal represents the video bit 4; in 10-bit video output mode: this
signal represents the video bit 6
MSB 4 of expansion-port data: in 8-bit video output mode: this
signal represents the video bit 3; in 10-bit video output mode: this
signal represents the video bit 5
MSB 5 of expansion-port data: in 8-bit video output mode: this
signal represents the video bit 2; in 10-bit video output mode: this
signal represents the video bit 4
MSB 6 of expansion-port data: in 8-bit video output mode: this
signal represents the video bit 1; in 10-bit video output mode: this
signal represents the video bit 3
expansion-port data: in 8-bit video output mode: this signal
represents the video bit 0 (LSB); in 10-bit video output mode: this
signal represents the video bit 2
SAF7115_1
Product data sheet
Rev. 01 — 15 October 2008
© NXP B.V. 2008. All rights reserved.
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