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PDF 24WC08 Data sheet ( Hoja de datos )
| Número de pieza | 24WC08 | |
| Descripción | CAT24WC08 | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 24WC08 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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CAT24WC01/02/04/08/16
wCww.DAataTShe2et4U4.coWm C01/02/04/08/16
1K/2K/4K/8K/16K-Bit Serial E2PROM
FEATURES
s 400 KHZ I2C Bus Compatible*
s 1.8 to 6.0Volt Operation
s Low Power CMOS Technology
s Hardware Write Protect
s Page Write Buffer
DESCRIPTION
s Self-Timed Write Cycle with Auto-Clear
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
s 8-pin DIP, 8-pin SOIC, 8 pin TSSOP or 14-pin
SOIC Package
s Commercial, Industrial and Automotive
Temperature Ranges
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K-
bit Serial CMOS E2PROM internally organized as 128/
256/512/1024/2048 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The CAT24WC01/02 features
an 8-byte page write buffer, and the CAT24WC04/08/16
features an 16-byte page write buffer. The device oper-
ates via the I2C bus serial interface, has a special write
protection feature, and is available in 8-pin DIP, 8-pin
SOIC, 8-pin TSSOP or 14-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J14)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOIC Package (J)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
NC 1 14 NC
A0 2 13 VCC
A1 3 12 TEST
NC 4 11 NC
A2 5 10 SCL
VSS
6
9 SDA
NC 7
8 NC
5027 FHD F01
TSSOP Package (U)
(* Available for 24WC01 and 24WC02 only)
5020 FHD F01
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SDA
START/STOP
LOGIC
XDEC
E2PROM
CONTROL
WP LOGIC
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2 Device Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +1.8V to +6.0V Power Supply
VSS Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 1997 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
24WCXX F03
Stock No. 21003-03 12/97
1 page  
CAT24WC01/02/04/08/16
using either 24WC01 or 24WC02 device. All three
address pins are used for these densities. If only one
w2w4wW.DCat0a2Shiseeat4dUd.rceosmsed on the bus, all three address pins
(A0, A1and A2) can be left floating or connected to VSS.
If only one 24WC01 is addressed on the bus, all three
address pins (A0, A1and A2) must be connected to VSS.
A total of four devices can be addressed on a single bus
when using 24WC04 device. Only A1 and A2 address
pins are used with this device. The A0 address pin can
be tied to VSS or left floating. If only one 24WC04 is being
addressed on the bus, the address pins (A1 and A2) can
be left floating or connected to VSS.
Only two devices can be cascaded when using 24WC08.
The only address pin used with this device is A2. The
other two address pins and can be tied to VSS or left
floating. If only one 24WC08 is being addressed on the
bus, the address pin (A2) can be left floating or con-
nected to VSS.
The 24WC16 is a stand alone device. In this case, all
address pins (A0, A1and A2) can be tied to VSS or left
floating.
WP: Write Protect
If the WP pin is tied to VCC the entire memory array
becomes Write Protected (READ only). When the WP
pin is tied to VSS or left floating normal read/write opera-
tions are allowed to the device.
I2C BUS PROTOCOL
The following defines the features of the I2C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
Figure 4. Acknowledge Timing
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC01/02/04/08/16
monitor the SDA and SCL lines and will not respond until
this condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5).
The next three significant bits (A2, A1, A0) are the device
address bits and define which device or which part of the
device the Master is accessing. Up to eight CAT24WC01/
02, four CAT24WC04, two CAT24WC08, and one
CAT24WC16 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC01/02/04/08/16 monitors
the bus and responds with an acknowledge (on the SDA
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
1
89
ACKNOWLEDGE
5020 FHD F06
Stock No. 21003-03 12/97
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 24WC08.PDF ] | |
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