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PDF 2S15902FP Data sheet ( Hoja de datos )

Número de pieza 2S15902FP
Descripción 6ch Electronic Volume
Fabricantes Renesas Technology 
Logotipo Renesas Technology Logotipo



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No Preview Available ! 2S15902FP Hoja de datos, Descripción, Manual

R2S15902FP
www.DataSheet4U.com
6ch Electronic Volume with 4 Input Selector
REJ03F0152-0100
Rev.1.0
Nov.22.2005
Description
R2S15902FP is an audio signal processor for home audio. This IC contains 6 channels electronic volume, gain control,
input selector and 2 band tone control.
Features
6 channels independent electronic volume (0 to –99dB/1dBstep, –dB)
6 channels independent gain control (0 to +14dB/ 2dB step)
L/R channel 4 input selector (Input gain: 0 to +14dB/ 2dB step)
Multi channel input: 6 channels input
Tone control Bass: –14 to + 14dB(2dB step),
Treble: –14 to + 14dB(2dB step)
Can use 1 input for REC output (REC output gain: 0, +2, +4, +6dB)
Built-in ADC output (Input Att: 0/ –6/ –12/ –18dB)
Built-in L+R/ L–R block
Built-in digital power supply
Recommended Operating Condition
Supply voltage range VCC = 8.0V to 10.0V: 9.0V(typ)
Application
Receiver, AV amp, Home theater, Mini stereo etc.
System Block Diagram
1
Lch 2
3
1
Rch 2
3
REC OUT
(4)
Multi Multi
Rin Lin
DGND
Lch Tone Rch Tone
CLOCK DATA
REC
Gain
Input
ATT
REC
Gain
Input
ATT
Input Gain
Input Gain
Volume
Volume
LoSL
SLin
Lch
+
-
(L -R)
MSLin
ADCL
(L-R) SRin
MSRin
Rch
(L+R)
+
-
LoSR
ADCR
(L+R)
Cin
MCin
SWin
MSWin
Tone
Bass&
Treble
Bass&
Treble
Volume
Volume
Volume
Volume
MCU I/F
Gain Control
Lout
Gain Control
Rout
Gain Control
SLout
Gain Control
SRout
Gain Control
Cout
Gain Control
SWout
(4)
REC OUT
Vref
AGND
VCC
Rev.1.0 Nov 22, 2005 page 1 of 15

1 page




2S15902FP pdf
R2S15902FP
Relationship Between Data and Clock
www.DaDtaaStaheseigt4nUa.cl oismread at the rising edge of CLOCK.
DATA
D0
D1
D2
D3
Make "H" at the timing which
DATA of D0-D23 make latch.
D21 D22 D23
CLOCK
When DATA is "H", latch signal is
created at the falling edge of CLOCK.
When CLOCK is "L" and latch signal is created,
latch signal is read at the falling edge of DATA.
Clock and Data Timings
DATA
75%
25%
(D0 to D23)
t cr
75%
50%
25%
CLOCK
tSLD tHLD tSHD tHHD
tr tf
tWHC
tWLC
LATCH
tSLD tHLD
tSC
Timing Definition of Digital Block
Parameter
CLOCK cycle time
CLOCK pulse width ("H" level)
CLOCK pulse width ("L" level)
Rising time of clock and data
Falling time of clock and data
DATA setup time (Rising time of clock)
DATA setup time (Falling time of clock)
DATA hold time ("H" level)
DATA hold time ("L" level)
CLOCK setup time
Symbol
tcr
tWHC
tWLC
tr
tf
tSHD
tSLD
tHHD
tHLD
tSC
Limits
Min Typ Max
8 ⎯⎯
3.2
3.2
⎯ ⎯ 0.8
⎯ ⎯ 0.8
1.6
1.6
1.6
1.6
1.6
Unit
µs
Rev.1.0 Nov 22, 2005 page 5 of 15

5 Page





2S15902FP arduino
R2S15902FP
Lch D3b D4b D5b
Rch D13b
D14b
D15b
AwwTwT.DataCSchheet4U.comD3c
SWch
D13c
D4c
D14c
D5c
D15c
SLch
D3d
D4d
D5d
SRch
D13d
D14d
D15d
–91dB
1
0
1
–92dB
1
0
1
–93dB
1
0
1
–94dB
1
0
1
–95dB
1
0
1
–96dB
1
1
0
–97dB
1
1
0
–98dB
1
1
0
–99dB
1
1
0
dB 1 1 1/0
Note: No guarantee except for these codes.
D6b
D16b
D6c
D16c
D6d
D16d
1
1
1
1
1
0
0
0
0
1/0
D7b
D17b
D7c
D17c
D7d
D17d
0
1
1
1
1
0
0
0
0
1
D8b
D18b
D8c
D18c
D8d
D18d
1
0
0
1
1
0
0
1
1
1/0
D9b
D19b
D9c
D19c
D9d
D19d
1
0
1
0
1
0
1
0
1
1/0
Electrical Characteristics
Unless otherwise noted, Ta = 25°C, VCC = 9V, f = 1kHz, Volume = 0dB, Input selector = IN1, Input gain = 0db,
Gain control = 0dB, ADC input ATT = 0dB, Tone = Bypass, L/R input = Selector in, SL/SR/C/SW input = L±R in
(1) Power supply characteristics
Parameter
Analog power supply circuit current
Symbol
ICC
Limits
Min Typ Max
35 55
Unit Test condition
mA With VCC = 9V
VCC current, when no signal is provided
Rev.1.0 Nov 22, 2005 page 11 of 15

11 Page







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