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PDF IDT72V3631 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V3631 | |
| Descripción | (IDT72V36x1) 3.3 VOLT CMOS SyncFIFOTM | |
| Fabricantes | Integrated Device Technology | |
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3.3 VOLT CMOS SyncFIFOTM
512 x 36
1,024 x 36
2,048 x 36
IDT72V3631
IDT72V3641
IDT72V3651
FEATURES
• Storage capacity:
IDT72V3631 - 512 x 36
IDT72V3641 - 1,024 x 36
IDT72V3651 - 2,048 x 36
• Supports clock frequencies up to 67 MHz
• Fast access times of 10ns
• Free-running CLKA and CLKB can be asynchronous or coinci-
dent (permits simultaneous reading and writing of data on a
single clock edge)
• Clocked FIFO buffering data from Port A to Port B
• Synchronous read retransmit capability
• Mailbox register in each direction
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• Input Ready (IR) and Almost-Full (AF) flags synchronized by
CLKA
• Output Ready (OR) and Almost-Empty (AE) flags synchronized
by CLKB
• Available in 132-pin plastic quad flat package (PQFP) or space-
saving 120-pin thin quad flat package (TQFP)
• Pin and functionally compatible versions of the 5V operating
IDT723631/723641/723651
• Easily expandable in width and depth
• Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION
The IDT72V3631/72V3641/72V3651 are pin and functionally compatible
versons of the IDT723631/723641/723651, designed to run off a 3.3V supply
forexceptionallylow-powerconsumption. Thesedevicesaremonolithichigh-
speed,low-power,CMOSclockedFIFOmemory. Itsupportsclockfrequencies
upto67MHzandhasreadaccesstimesasfastas10ns. The512/1,024/2,048
x36dual-portSRAMFIFObuffersdatafromportAtoPortB. TheFIFOmemory
has retransmit capability, which allows previously read data to be accessed
again. The FIFO operates in First Word Fall Through mode and has flags to
indicate empty and full conditions and conditions and two programmable flags
(Almost-Full and Almost-Empty)to indicate when a selectednumber ofwords
is stored in memory. Communication between each port may take place with
FUNCTIONAL BLOCK DIAGRAM
MBF1
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST
Reset
Logic
Mail 1
Register
RAM ARRAY
512 x 36
1,024 x 36
2,048 x 36
RTM
A0 - A35
IR
AF
36
Write Read
Pointer Pointer
Status Flag
Logic
RFM
B0 - B35
OR
AE
FS0/SD
FS1/SEN
Flag Offset
Registers
10
Mail 2
Register
MBF2
IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
11
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
4658 drw 01
NOVEMBER 2003
DSC-4658/1
1 page  
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(2)
Sywmwbwo.Dl ataSheet4U.com
Rating
Commercial
Unit
VCC Supply Voltage Range
–0.5 to +4.6
V
VI(2) Input Voltage Range
–0.5 to VCC+0.5(3)
V
VO(2) Output Voltage Range
–0.5 to VCC+0.5
V
IIK Input Clamp Current, (VI < 0 or VI > VCC)
±20 mA
IOK Output Clamp Current, (VO = < 0 or VO > VCC)
±50 mA
IOUT Continuous Output Current, (VO = 0 to VCC)
±50 mA
ICC Continuous Current Through VCC or GND
±400 mA
TSTG Storage Temperature Range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
3. Control Inputs: maximum VI = 5.0V.
RECOMMENDED OPERATING
CONDITIONS
Symbol
Parameter
Min. Typ.
Max. Unit
VCC Supply Voltage
3.0 3.3
3.6 V
VIH HIGH Level Input Voltage 2 — VCC+0.5 V
VIL LOW-LevelInputVoltage
——
0.8 V
IOH HIGH-Level Output Current —
—
–4 mA
IOL LOW-LevelOutputCurrent
—
—
8 mA
TA OperatingFree-air
Temperature
0—
70 °C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3631
IDT72V3641
IDT72V3651
Commercial
tCLK = 15, 20 ns
Symbol
Parameter
Test Conditions
Min. Typ.(1) Max.
VOH Output Logic "1" Voltage
VCC = 3.0V,
IOH = –4 mA
2.4 — —
VOL Output Logic "0" Voltage
VCC = 3.0V,
IOL = 8 mA
— — 0.5
ILI Input Leakage Current (Any Input)
VCC = 3.6V,
VI = VCC or 0
— — ±5
ILO
ICC2(2)
Output Leakage Current
Standby Current
VCC = 3.6V,
VCC = 3.6V,
VO = VCC or 0
VI = VCC –0.2V or 0
— — ±5
— — 400
CIN Input Capacitance
VI = 0,
f = 1 MHz
—4—
COUT
Output Capacitance
VO = 0,
f = 1 MHZ
—8—
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
5
Unit
V
V
µA
µA
µA
pF
pF
5 Page 
IDT72V3631/72V3641/72V3651
3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36
grammingsection). TheAEflagisLOWwhentheFIFOcontainsXorlesswords
andisHIGHwhentheFIFOcontains(X+1)ormorewords. Adatawordpresent
in the FIFO output register has been read from memory.
TwwowLwO.DWa-ttaoS-HhIeGeHt4tUra.cnosmitions of CLKB are required after a FIFO write for
the AE flag to reflect the new level of fill; therefore, the AE flag of a FIFO containing
(X+1) or more words remains LOW if two cycles of CLKB have not elapsed since
thewritethatfilledthememorytothe(X+1)level. An AEflagissetHIGHbythe
second LOW-to-HIGH transition of CLKB after the FIFO write that fills memory
to the (X+1) level. A LOW-to-HIGH transition of CLKB begins the first
synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills
the FIFO to (X+1) words. Otherwise, the subsequent CLKB cycle may be the
first synchronization cycle (see Figure 9).
ALMOST-FULL FLAG (AF)
The Almost-Full flag of a FIFO is synchronized to the port Clock that writes
data to its array (CLKA). The state machine that controls an AF flag monitors
a write-pointer and read-pointer comparator that indicates when the FIFO
memorystatusisalmost-full,almost-full-1,oralmost-full-2. Thealmost-fullstate
isdefinedbythecontentsofregisterY. Thisregisterisloadedwithapresetvalue
during a FIFO reset, programmed from port A, or programmed serially (see
Almost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection). TheAFflag
is LOW when the number of words in the FIFO is greater than or equal to (512-Y),
(1,024-Y), OR (2,048-Y) for the IDT72V3631, IDT72V3641, or IDT72V3651,
respectively. The AF flag is HIGH when the number of words in the FIFO is
less than or equal to [512-(Y+1)], [1,024-(Y+1)], or [2,048-(Y+1)] for the
IDT72V3631, IDT72V3641, or IDT72V3651, respectively. A data word
present in the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of CLKA are required after a FIFO read for
itsAFflagtoreflectthenewleveloffill. Therefore,theAFflagofaFIFOcontaining
[512/1,024/2,048-(Y+1)] or less words remains LOW if two cycles of CLKA have
not elapsed since the read that reduced the number of words in memory to [512/
1,024/2,048-(Y+1)]. An AF flag is set HIGH by the second LOW-to-HIGH
transition of CLKA after the FIFO read that reduces the number of words in
memory to [512/1,024/2,048-(Y+1)]. A LOW-to-HIGH transition of CLKA
begins the first synchronization cycle if it occurs at time tSKEW2 or greater after
thereadthatreducesthenumberofwordsinmemoryto[512/1,024/2,048-(Y+1)].
Otherwise, the subsequent CLKA cycle may be the first synchronization cycle
(see Figure 10).
COMMERCIALTEMPERATURERANGE
SYNCHRONOUS RETRANSMIT
The synchronous retransmit feature of these devices allow FIFO data to be
read repeatedly starting at a user-selected position. The FIFO is first put into
retransmit mode to select a beginning word and prevent ongoing FIFO write
operationsfromdestroyingretransmitdata. Datavectorswithaminimumlength
ofthreewordscanretransmitrepeatedlystartingattheselectedword. TheFIFO
can be taken out of retransmit mode at any time and allow normal device
operation.
The FIFO is put in retransmit mode by a LOW-to-HIGH transition on CLKB
when the retransmit mode (RTM) input is HIGH and OR is HIGH. The rising
CLKB edge marks the data present in the FIFO output register as the first
retransmit data. The FIFO remains in retransmit mode until a LOW-to-HIGH
transition occurs while RTM is LOW.
When two or more reads have been done past the initial marked retransmit
word, a retransmit is initiated by a LOW-to-HIGH transition on CLKB when the
read-from-mark (RFM) input is HIGH. This rising CLKB edge shifts the first
retransmit word to the FIFO output register and subsequent reads can begin
immediately. Retransmit loops can be done endlessly while the FIFO is in
retransmit mode. RFM must be LOW during the CLKB rising edge that takes
the FIFO out of retransmit mode (see Figure 11).
When the FIFO is put into retransmit mode, it operates with two read pointers.
The current read pointer operates normally, incrementing each time when a
newwordisshiftedtotheFIFOoutputregister. Thisreadpointerpositionis used
by the OR andAE flags. The shadow read pointer stores the memory location
at the time the device is put into retransmit mode and does not change until the
deviceistakenoutofretransmitmode. Theshadowreadpointerpositionisused
by the IR andAF flags. DatawritescanproceedwhiletheFIFOisinretransmit
mode, but AF is set LOW by the write that stores (512-Y), (1,024 - Y), or
(2,048-Y) words after the first retransmit word for the IDT72V3631, IDT72V3641,
or IDT72V3651, respectively. The IR flag is set LOW by the 512th, 1,024th,
or 2,048th write after the first retransmit word for the IDT72V3631, IDT72V3641,
or IDT72V3651, respectively.
When the FIFO is in retransmit mode and RFM is HIGH, a rising CLKB edge
loads the current read pointer with the shadow read-pointer value and the OR
flagreflectsthenewleveloffillimmediately. IftheretransmitchangestheFIFO
status out of the almost-empty range, up to two CLKB rising edges after the
retransmit cycle are needed to switch AE high (see Figure 12). The rising CLKB
TABLE 4 — FIFO FLAG OPERATION
IDT72V3631(3)
Number of Words in the FIFO(1,2)
IDT72V3641(3)
IDT72V3651(3)
Synchronized
to CLKB
OR AE
Synchronized
to CLKA
AF IR
0 0 0 L L HH
1 to X
1 to X
1 to X
H L HH
(X+1) to [512-(Y+1)]
(X+1) to [1,024-(Y+1)]
(X+1) to [2,048-(Y+1)]
H
H HH
(512-Y) to 511
(1,024-Y) to 1,023
(2,048-Y) to 2,047
H H LH
512
1,024
2,048
H H LL
NOTES:
1. When a word is present in the FIFO output register, its previous memory location is free.
2. Data in the output register does not count as a "word i n FIFO memory". Since in FWFT mode, the first words written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the memory count.
3. X is the Almost-Empty Offset for AE. Y is the Almost-Full Offset for AF.
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet IDT72V3631.PDF ] | |
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