PDF FMP1617CCx Data sheet ( Hoja de datos )

Número de pieza	FMP1617CCx
Descripción	1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM
Fabricantes	FIDELIX
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No Preview Available ! FMP1617CCx Document Title 1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM www.DataSheet4U.com Revision History Revision No. 0.0 0.1 History Initial Draft Revised P/N according to the new P/N system CMOS LPRAM Draft date Apr. 19th, 2006 Jun.01st , 2006 Remark Preliminary Preliminary 1 Revision 0.1 Jun. 2006 1 page FMP1617CCx AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) wInwpuwt.pDualstaeSlehveeel :t40U.2.ctoomVCC-0.2V Input rising and falling time : 5ns Input and output reference voltage : 0.5*VCCQ Output load(see right) : CL=30pF+1TTL CMOS LPRAM 30pf 1TTL AC CHARACTERISTICS(VCC=1.7V~1.95V) Parameter List Symbol Read Write Page Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output /UB, /LB Access Time Chip Select to Low-Z Output /UB, /LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High- Z Output /UB, /LB Disable to High- Z Output Output Disable to High- Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write /UB, /LB Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Page Mode Cycle Time Page Mode Address Access Time Maximum Cycle Time /CS High Pulse Width tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW tPC tPAA tMRC tCP Speed Bins 70ns 85ns Min Max Min Max 70 20k 85 20k - 70 - 85 - 70 - 85 - 25 - 30 - 70 - 85 10 - 10 - 10 - 10 - 5-5- 0505 0505 0505 5-5- 70 20k 85 20k 60 - 70 - 0-0- 60 - 70 - 60 - 70 - 50 - 60 - 0-0- 0505 20 - 20 - 0-0- 5-5- 25 - 30 - - 25 - 30 - 20k - 20k 10 - 10 - 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 Revision 0.1 Jun. 2006 5 Page FMP1617CCx 3. Deep Power Down Mode Entry/Exit www.DataSheet4U.com tWC A4 /CS tAS(3) tCW(2 ) tAW /UB, /LB tBW /WE /ZZ tZZWE tWP(1) tWR(4 ) tZZmin CMOS LPRAM tR Next Cycle Register Write(DPD) Deep Power down start Parameter tZZWE tR(Deep Power Down Mode only) tZZmin Description ZZ low to Write Enable Low Operation Recovery Time Low Power Mode Time Deep Power down exit Min Max Units 0 1 us 200 - us 10 - us 4. Address Information Partial Array Refresh Mode (A3=0, A4=1) A2 A1,A0 0 11 Refresh Section 1/4 0 10 1/2 X 00 1 11 1 10 Full 1/4 1/2 Address 00000h-3FFFFh 00000h-7FFFFh 00000h-FFFFFh C0000h-FFFFFh 80000h-FFFFFh Size 256Kbx16 512Kbx16 1Mbx16 256Kbx16 512Kbx16 Density 4Mb 8Mb 16Mb 4Mb 8Mb Reduced Memory Size Mode (A3=1, A4=1) A2 A1,A0 0 11 Refresh Section 1/4 0 10 1 11 1 10 1/2 1/4 1/2 Address 00000h-3FFFFh 00000h-7FFFFh C0000h-FFFFFh 80000h-FFFFFh Size 256Kbx16 512Kbx16 256Kbx16 512Kbx16 Density 4Mb 8Mb 4Mb 8Mb 11 Revision 0.1 Jun. 2006 11 Page

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