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PDF M67025E Data sheet ( Hoja de datos )

Número de pieza M67025E
Descripción Tolerant High Speed 8 Kb x 16 Dual Port RAM
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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Features
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Wide Temperature Range: -55°C to +125°C
Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility
Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using
More Than One Device
On-chip Arbitration Logic
Versatile Pin Select for Master or Slave:
– M/S = H for Busy Output Flag On Master
– M/S = L for Busy Input Flag On Slave
INT Flag for Port to Port Communication
Full Hardware Support of Semaphore Signaling Between Ports
Fully Asynchronous Operation From Either Port
Battery Back-up Operation: 2V Data Retention
TTL Compatible
Single 5V + 10% Power Supply
QML Q and V with SMD 5962-91617
Introduction
The M67025E is a very low power CMOS dual port static RAM organized as 8192 bit
× 16. The product is designed to be used as a stand-alone 16-bit dual port RAM or as
a combination MASTER/SLAVE dual port for 32-bit or more width systems. The Atmel
MASTER/SLAVE dual port approach in memory system applications results in full
speed, error free operation without the need of an additional discrete logic.
Master and slave devices provide two independent ports with separate control,
address and I/O pins that permit independent, asynchronous access for reads and
writes to any location in the memory. An automatic power down feature controlled by
CS permits the on-chip circuitry of each port in order to enter a very low stand by
power mode.
Using an array of eight transistors (8T) memory cell, the M67025E combines an
extremely low standby supply current (typ = 1.0 µA) with a fast access time at 30 ns
over the full temperature range. All versions offer battery backup data retention capa-
bility with a typical power consumption at less than 5 µW.
For military/space applications that demand superior levels of performance and reli-
ability the M67025E is processed according to the methods of the latest revision of the
MIL PRF 38635 (Q and V) and/or ESA SCC 9000.
Rad. Tolerant
High Speed
8 Kb x 16
Dual Port RAM
M67025E
Rev. 4146J–AERO–06/03
1

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M67025E pdf
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Semaphore Logic
How The Semaphore
Flags Work
The write pulse to the SLAVE must be inhibited by the MASTER’s maximum arbitration
time. If a conflict then occurs, the write to the SLAVE will be inhibited because of the
MASTER’s BUSY signal.
The M67025E is an extremely fast dual-port 4 Kb × 16 CMOS static RAM with an additional
locations dedicated to binary semaphore flags. These flags allow either of the processors on the
left or right side of the dual-port RAM to claim priority over the other for functions defined by the
system software. For example, the semaphore flag can be used by one processor to inhibit the
other from accessing a portion of the dual-port RAM or any other shared resource.
The dual-port RAM has a fast access time, and the two ports are completely indepen-
dent of each another. This means that the activity on the left port cannot slow the access
time of the right port. The ports are identical in function to standard CMOS static RAMs
and can be read from, or written to, at the same time with the only possible conflict aris-
ing from simultaneous writing to, or a simultaneous READ/WRITE operation on, a non-
semaphore location. Semaphores are protected against such ambiguous situations and
may be used by the system program to prevent conflicts in the non-semaphore segment
of the dual-port RAM. The devices have an automatic power-down feature controlled by
CS, the dual-port RAM select and SEM, the semaphore enable. The CS and SEM pins control
on-chip-power-down circuitry that permits the port concerned to go into stand-by mode when
not selected. This conditions is shown in Table 1 where CS and SEM are both high.
Systems best able to exploit the M67025E are based around multiple processors or con-
trollers and are typically very high-speed, software controlled or software-intensive
systems. These systems can benefit from the performance enhancement offered by the
M67025 hardware semaphores, which provide a lock-out mechanism without the need
for complex programming.
Software handshaking between processors offers the maximum level of system flexibil-
ity by permitting shared resources to be allocated in varying configurations. The
M67025E does not use its semaphore flags to control any resources through hardware,
thus allowing the system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more usual methods of hardware
arbitration is that neither processor ever incurs wait states. This can prove to be a con-
siderable advantage in very high speed systems.
The semaphore logic is a set of eight latches independent of the dual-port RAM. These
latches can be used to pass a flag or token, from one port to the other to indicate that a
shared resource is in use. The semaphore provides the hardware context for the “Token
Passing Allocation’ method of use assignment. This method uses the state of a sema-
phore latch as a token indicating that a shared resource is in use. If the left processor
needs to use a resource, it requests the token by setting the latch. The processor then
verifies that the latch has been set by reading it. If the latch has been set the processor
assumes control over the shared resource. If the latch has not been set, the left proces-
sor has established that the right processor had set the latch first, has the token and is
using the shared resource. The left processor may then either repeatedly query the sta-
tus of the semaphore, or abandon its request for the token and perform another
operation whilst occasionally attempting to gain control of the token through a set and
test operation. Once the right side has relinquished the token the left side will be able to
take control of the shared resource.
The semaphore flags are active low. A token is requested by writing a zero to a sema-
phore latch, and is relinquished again when the same side writes a one to the latch.
5 M67025E
4146J–AERO–06/03

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M67025E arduino
Electrical Characteristics
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Absolute Maximum Ratings
Supply voltage (VCC-GND): ............................... -0.5V to 7.0V
Input or output voltage applied: (GND - 0.5V) to (VCC + 0.5V)
Storage temperature: ..................................... -65°C to +150°C
*NOTE:
Stresses greater than those listed under Absolute Max-
imum Ratings may cause permanent damage to the
device.This is a stress rating only and functional opera-
tion of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC Parameters
Table 6. DC Test Conditions
TA = -55°C to + 125°C; Vss = 0V; Vcc = 4.5V to 5.5V
Parameter Description
67025-30
67025-45
Unit
ICCSB(1)
Standby supply current (Both ports TTL level inputs)
10
10 mA
ICCSB1(2)
Standby supply current (Both ports CMOS level
inputs)
500
500
µA
ICCOP(3)
Operating supply current (Both ports active)
320 260 mA
ICCOP1(4)
Operating supply current (One port active - One
port standby)
200
180
mA
Notes:
1. CSL = CSR > 2.2V.
2. CSL = CSR > VCC - 0.2V.
3. Both ports active - Maximum frequency - Outputs open - OE = VIH.
4. One port active (f = fMAX) - Output open - One port stand-by TTL or CMOS Level Inputs - CSL = CSR > 2.2V
Value
Max
Max
Max
Max
Parameter
IL I/O (1)
VIL (2)
VIH(2)
VOL (3)
VOH(3)
C IN
C OUT
Description
Input/Output leakage current
Input low voltage
Input high voltage
Output low voltage (I/O0 - I/O15)
Output high voltage
Input capacitance
Output capacitance
67025E
±5
0.8
2.2
0.4
2.4
5
7
Unit
µA
V
V
V
V
pF
pF
Value
Max
Max
Min.
Max
Min.
Max
Max
1. Vcc = 5.5V, Vin = Gnd to Vcc, CS = VIH, Vout = 0 to Vcc.
2. VIH max = Vcc + 0.5V, VIL min = -0.5V or -1V pulse width 50 ns.
3. Vcc Min., IOL = 4 mA, IOH = -4 mA.
11 M67025E
4146J–AERO–06/03

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