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Número de pieza | KAD5512P-50 | |
Descripción | 500MSPS A/D Converter | |
Fabricantes | Kenet | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de KAD5512P-50 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
No Preview Available ! KAD5512P-50 Preliminary
www.DataSheet4U.com 12-Bit, 500MSPS A/D Converter
General Description
The KAD5512P-50 is a low-power, high-performance,
12-bit, 500MSPS analog-to-digital converter
designed with Kenet’s proprietary FemtoCharge®
technology on a standard CMOS process. The
KAD5512P-50 is part of a pin-compatible portfolio of
10, 12 and 14-bit A/Ds with sample rates ranging
from 125MSPS to 500MSPS.
The device utilizes two time-interleaved 12-bit,
250MSPS A/D cores to achieve the ultimate sample
rate of 500MSPS. A single 500MHz conversion clock is
presented to the converter, and all interleave
clocking is managed internally.
A serial peripheral interface (SPI) port allows for
extensive configurability, as well as fine control of
matching characteristics (gain, offset, skew)
between the two converter cores. These
adjustments allow the user to minimize spurs
associated with the interleaving process.
Digital output data is presented in selectable LVDS
or CMOS formats. The KAD5512P-50 is available in a
72-contact QFN package with an exposed paddle.
Performance is specified over the full industrial
temperature range (-40 to +85°C).
Features
CLKP
CLKN
VINP
VINN
VCM
VREF
VREF
1.25 V
Key Specifications
• SNR = 64.3dBFS for fIN = 250MHz (-1dBFS)
• SFDR = 80dBc for fIN = 250MHz (-1dBFS)
• Power consumption = 400mW
CLKOUTP
CLKOUTN
D[11:0]P
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
• Programmable gain, offset and skew control
• 1.3 GHz analog input bandwidth
• 52fs Clock Jitter
• Over-range indicator
• Selectable Clock Divider: ÷1 or ÷2
• Clock Phase Selection
• Nap and Sleep modes
• Two’s complement, Gray code or Binary data
format
• DDR LVDS-compatible or LVCMOS outputs
• Programmable Built-in Test Patterns
• 1.8V Analog and Digital Supplies
Applications
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• High-Performance Data Acquisition
Pin-Compatible Family
Model
KAD5514P-25
KAD5514P-21
KAD5514P-17
KAD5514P-12
KAD5512P-50
KAD5512P-25, KAD5512HP-25
KAD5512P-21, KAD5512HP-21
KAD5512P-17, KAD5512HP-17
KAD5512P-12, KAD5512HP-12
Resolution
14
14
14
14
12
12
12
12
12
Speed (MSPS)
250
210
170
125
500
250
210
170
125
KAD5510P-50
10 500
300 Unicorn Park Dr., Woburn, MA 01801
Sales: 1-781-497-0060
FemtoCharge is a registered trademark of Kenet, Inc.
Rev 0.5.1 Preliminary
Copyright © 2007, Kenet, Inc.
Page 1
1 page KAD5512P-50
Digital Specifications
www.DataSheet4U.com
Parameter
Inputs
Input Current High (RESETN)
Input Current Low (RESETN)
Input Current High (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT )
Input Current Low (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT )
Input Capacitance
LVDS Outputs
Differential Output Voltage
Output Offset Voltage
Output Rise Time
Output Fall Time
CMOS Outputs
Voltage Output High
Voltage Output Low
Output Rise Time
Output Fall Time
Symbol Conditions
IIH VIN = 1.8V
IIL VIN = 0V
IIH
IIL
CDI
VT
VOS
tR
tF
VOH
VOL
tR
tF
Timing Diagrams
Min Typ Max Units
0 1 10
25 50 75
TBD 25 TBD
TBD 25 TBD
3
210
TBD
500
500
µA
µA
µA
µA
pF
mV
mV
ps
ps
OVDD-0.1
0.1
TBD
TBD
V
V
ns
ns
Figure 1. LVDS Timing Diagram
Rev 0.5.1 Preliminary
Figure 2. CMOS Timing Diagram
Page 5
5 Page KAD5512P-50
Typwwiwc.DaatalSPheeet4rUf.ocomrmance Curves
TBD
Figure 10. Power vs. fSAMPLE
TBD
Figure 12. Integral Nonlinearity
TBD
Figure 14. Noise Histogram
Rev 0.5.1
TBD
Figure 11. Differential Nonlinearity
TBD
Figure 13. SNR & SFDR vs. VCM
TBD
Figure 15. Single Tone Spectrum @ 10 MHz
Page 11
11 Page |
Páginas | Total 28 Páginas | |
PDF Descargar | [ Datasheet KAD5512P-50.PDF ] |
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