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PDF KAD5512P Data sheet ( Hoja de datos )

Número de pieza KAD5512P
Descripción 250/210/170/125MSPS ADC
Fabricantes Intersil Corporation 
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Data Sheet
Low Power 12-Bit, 250/210/170/125MSPS
ADC
The KAD5512P is the low-power member of the KAD5512
family of 12-bit analog-to-digital converters. Designed with
Intersil’s proprietary FemtoCharge™ technology on a
standard CMOS process, the family supports sampling rates
of up to 250MSPS. The KAD5512P is part of a
pin-compatible portfolio of 10, 12 and 14-bit A/Ds with
sample rates ranging from 125MSPS to 500MSPS.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5512P is available in 72- and 48-contact
QFN packages with an exposed paddle. Operating from a
1.8V supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
Key Specifications
• SNR = 65.1dBFS for fIN = 124MHz (-1dBFS)
• SFDR = 80dBc for fIN = 124MHz (-1dBFS)
• Power Consumption
- 254/207mW @ 250/125MSPS (SDR Mode)
- 220/176mW @ 250/125MSPS (DDR Mode)
CLKP
CLKN
VINP
VINN
VCM
Clock
Generation
SHA
+
1.25 V
12-bit
250 MSPS
ADC
SPI
Control
Digital
Error
Correction
LVDS/CMOS
Drivers
CLKOUTP
CLKOUTN
D[11:0]P
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
December 5, 2008
KAD5512P
FN6807.0
Features
• Pin-Compatible with the KAD5512HP Family, Operating at
Half the Power
• Programmable Gain, Offset and Skew Control
• 1.3GHz Analog Input Bandwidth
• 60fs Clock Jitter
• Over-Range Indicator
• Selectable Clock Divider: ÷1, ÷2 or ÷4
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• SDR/DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
• Pb-Free (RoHS Compliant)
Applications
• Power Amplifier Linearization
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
• WiMAX and Microwave Receivers
Pin-Compatible Family
MODEL
KAD5514P-25
KAD5514P-21
KAD5514P-17
KAD5514P-12
KAD5512P-50
KAD5512P-25,
KAD5512HP-25
KAD5512P-21,
KAD5512HP-21
KAD5512P-17,
KAD5512HP-17
KAD5512P-12,
KAD5512HP-12
KAD5510P-50
RESOLUTION
14
14
14
14
12
12
12
12
12
10
SPEED
(MSPS)
250
210
170
125
500
250
210
170
125
500
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




KAD5512P pdf
KAD5512P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
www.DataSheet4U.com
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per
speed grade). (Continued)
KAD5512P-25
KAD5512P-21
KAD5512P-17
KAD5512P-12
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Integral Nonlinearity INL
±1.5 ±1.5 ±1.5 ±1.5 LSB
Minimum
Conversion Rate
(Note 6)
fS MIN
40 40 40 40 MSPS
Maximum
Conversion Rate
fS MAX
250 210 170 125 MSPS
Signal-to-Noise
Ratio
Signal-to-Noise and
Distortion
Effective Number of
Bits
Spurious-Free
Dynamic Range
Intermodulation
Distortion
Word Error Rate
SNR
SINAD
ENOB
SFDR
IMD
WER
fIN = 10MHz
fIN = 70MHz
fIN = 105MHz
fIN = 230MHz
fIN = 400MHz
fIN = 995MHz
fIN = 10MHz
fIN = 70MHz
fIN = 105MHz
fIN = 230MHz
fIN = 400MHz
fIN = 995MHz
fIN = 10MHz
fIN = 70MHz
fIN = 105MHz
fIN = 230MHz
fIN = 400MHz
fIN = 995MHz
fIN = 10MHz
fIN = 70MHz
fIN = 105MHz
fIN = 230MHz
fIN = 400MHz
fIN = 995MHz
fIN = 70MHz
fIN = 170MHz
65.2
65.1
63.0 65.1
64.8
64.2
61.4
65.0
65.0
62.5 64.7
64.5
63.2
53.9
10.5
10.5
10.1 10.5
10.4
10.2
8.7
84
84
70 80
77
71
57
-90.5
-86.0
10-12
65.8
65.7
64.0 65.6
65.7
66.5
66.7
63.5 66.2
66.2
10.8
10.8
10.3 10.7
10.7
84
83
70 80
76
TBD
TBD
10-12
66.2
66.2
64.5 66.0
66.1
67
66.9
64.0 66.7
66.6
10.8
10.8
10.3 10.8
10.8
85
82
70 80
77
TBD
TBD
10-12
66.7
66.6
64.8 66.4
66.3
65.4
62.4
67.4
67.3
64.3 67.0
66.8
64.4
54.0
10.9
10.9
10.4 10.8
10.8
10.4
8.7
85
83
70 80
79
74
55
-96.5
-93.0
10-12
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
Full Power
Bandwidth
FPBW
1.3 1.3 1.3 1.3 GHz
NOTES:
3. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital
output.
4. Nap Mode must be invoked using SPI. See “Nap/Sleep” on page 18 for more detail.
5. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to “Power-On Calibration”
on page 15 and “User-Initiated Reset” on page 16 for more details.
6. The DLL Range setting must be changed for low speed operation. See “Serial Peripheral Interface” on page 21 for more detail.
5 FN6807.0
December 5, 2008

5 Page





KAD5512P arduino
Pinout
www.DataSheet4U.com
KAD5512P
KAD5512P
(48 LD QFN)
TOP VIEW
AVDD
DNC
DNC
DNC
AVSS
VINN
VINP
AVSS
AVDD
VCM
DNC
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
KAD5512
48 QFN
Top View
Not to Scale
36 D4P
35 D4N
34 D3P
33 D3N
32 CLKOUTP
31 CLKOUTN
30 RLVDS
29 OVSS
28 D2P
27 D2N
26 D1P
25 D1N
FIGURE 4. PIN CONFIGURATION
11 FN6807.0
December 5, 2008

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