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PDF KAD2708C Data sheet ( Hoja de datos )

Número de pieza KAD2708C
Descripción 275/210/170/105MSPS A/D Converter
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! KAD2708C Hoja de datos, Descripción, Manual

KAD2708C
®
www.DataSheet4U.com
Data Sheet
8-Bit, 275/210/170/105MSPS A/D
Converter
The KAD2708C is the industry’s lowest power, 8-bit,
275MSPS, high performance Analog-to-Digital converter. It
is designed with Intersil’s proprietary FemtoCharge™
technology on a standard CMOS process. The KAD2708C
offers high dynamic performance (49.2dBFS SNR @
fIN = 138MHz) while consuming less than 265mW. Features
include an over-range indicator and a selectable divide-by-2
input clock divider. The KAD2708C is one member of a
pin-compatible family offering 8 and 10-bit ADCs with
sample rates from 105MSPS to 350MSPS and LVCMOS or
LVDS-compatible outputs (Table 1). This family of products
is available in 68-pin RoHS-compliant QFN packages with
exposed paddle. Performance is specified over the full
industrial temperature range (-40°C to +85°C).
CLK_P
CLK_N
Clock
Generation
INP
INN
VREF
VREFSEL
VCM
S/H
8-bit
275MSPS
ADC
8
LVCMOS
Drivers
1.21 V
+
CLKOUT
D7 – D0
OR
2SC
Ordering Information
PART NUMBER
SPEED
(MSPS)
TEMP.
RANGE
(°C) PACKAGE
PKG.
DWG. #
KAD2708C-27Q68 275 -40 to +85 68 Ld QFN L68.10x10B
KAD2708C-21Q68 210 -40 to +85 68 Ld QFN L68.10x10B
KAD2708C-17Q68 170 -40 to +85 68 Ld QFN L68.10x10B
KAD2708C-10Q68 105 -40 to +85 68 Ld QFN L68.10x10B
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
December 5, 2008
FN6812.0
Features
• On-Chip Reference
• Internal Track and Hold
• 1.5VP-P Differential Input Voltage
• 600MHz Analog Input Bandwidth
• Two’s Complement or Binary Output
• Over-Range Indicator
• Selectable ÷2 Clock Input
• LVCMOS Outputs
Applications
• High-Performance Data Acquisition
• Portable Oscilloscope
• Medical Imaging
• Cable Head Ends
• Power-Amplifier Linearization
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• Point-to-Point Microwave Systems
• Communications Test Equipment
Key Specifications
• SNR of 49.2dBFS at fS = 275MSPS, fIN = 138MHz
• SFDR of 66.6dBc at fS = 275MSPS, fIN = 138MHz
• Power Consumption 265mW at fS = 275MSPS
Pin-Compatible Family
TABLE 1. PIN-COMPATIBLE PRODUCTS
RESOLUTION, SPEED LVDS OUTPUTS LVCMOS OUTPUTS
8 Bits 350MSPS
KAD2708L-35
10 Bits 275MSPS
KAD2710L-27
KAD2710C-27
8 Bits 275MSPS
KAD2708L-27
KAD2708C-27
10 Bits 210MSPS
KAD2710L-21
KAD2710C-21
8 Bits 210MSPS
KAD2708L-21
KAD2708C-21
10 Bits 170MSPS
KAD2710L-17
KAD2710C-17
8 Bits 170MSPS
KAD2708L-17
KAD2708C-17
10 Bits 105MSPS
KAD2710L-10
KAD2710C-10
8 Bits 105MSPS
KAD2708L-10
KAD2708C-10
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




KAD2708C pdf
Timing Diagram
www.DataSheet4U.com
KAD2708C
INP
Sample N
INN
CLKN
CLKP
tA
CLKOUT
D[7:0]
L
tPID
tPCD
tPH
Data N-L
Data N-L+1
invalid
FIGURE 1. LVCMOS TIMING DIAGRAM
Timing Specifications
PARAMETER
Aperture Delay
RMS Aperture Jitter
Input Clock to Data Propagation Delay
Data Hold Time
Output Clock to Data Propagation Delay
Latency (Pipeline Delay)
Overvoltage Recovery
SYMBOL
tA
jA
tPID
tPH
tPCD
L
tOVR
MIN
3.5
-300
TYP
1.7
200
5.0
2.8
28
1
Thermal Impedance
PARAMETER
SYMBOL
Junction to Paddle (Note 1)
θJP
NOTE:
1. Paddle soldered to ground plane.
TYP
30
UNIT
°C/W
Data N
MAX
6.5
3.7
UNITS
ns
fs
ns
ps
ns
cycles
cycle
ESD
Electrostatic charge accumulates on humans, tools and
equipment and may discharge through any metallic package
contacts (pins, balls, exposed paddle, etc.) of an integrated
circuit. Industry-standard protection techniques have been
utilized in the design of this product. However, reasonable
care must be taken in the storage and handling of ESD
sensitive products. Contact Intersil for the specific ESD
sensitivity rating of this product.
5
FN6812.0
December 5, 2008

5 Page





KAD2708C arduino
KAD2708C
Functional Description
The KAD2708 is an eight bit, 275MSPS A/D converter in a
pipwewliwne.DdaatarSchheiteetc4tUu.rceo.mThe input voltage is captured by a
sample & hold circuit and converted to a unit of charge.
Proprietary charge domain techniques are used to compare
the input to a series of reference charges. These
comparisons determine the digital code for each input value.
The converter pipeline requires 24 sample clocks to produce
a result. Digital error correction is also applied, resulting in a
total latency of 28 clock cycles. This is evident to the user as
a latency between the start of a conversion and the data
being available on the digital outputs.
At start-up, a self-calibration is performed to minimize gain
and offset errors. The reset pin (RST) is initially held low
internally at power-up and will remain in that state until the
calibration is complete. The clock frequency should remain
fixed during this time.
Calibration accuracy is maintained for the sample rate at
which it is performed, and therefore should be repeated if the
clock frequency is changed by more than 10%. Recalibration
can be initiated via the RST pin, or power cycling, at any
time.
Reset
Recalibration of the ADC can be initiated at any time by
driving the RST pin low for a minimum of one clock cycle. An
open-drain driver is recommended.
The calibration sequence is initiated on the rising edge of
RST, as shown in Figure 21. The over-range output (OR) is
set high once RST is pulled low, and remains in that state
until calibration is complete. The OR output returns to
normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range in
order to observe the transition. If the input is in an
over-range state the OR pin will stay high and it will not be
possible to detect the end of the calibration cycle.
While RST is low, the output clock (CLKOUT) stops toggling
and is set low. Normal operation of the output clock resumes
at the next input clock edge (CLKP/CLKN) after RST is
deasserted. At 275MSPS the nominal calibration time is
~240ms.
CLKN
CLKP
RST
OR
CLKOUT
Calibration Time
Calibration Begins
Calibration Complete
Voltage Reference
The VREF pin is the full-scale reference, which sets the
full-scale input voltage for the chip and requires a bypass
capacitor of 0.1µF or larger. An internally generated
reference voltage is provided from a bandgap voltage buffer.
This buffer can sink or source up to 50µA externally.
An external voltage may be applied to this pin to provide a
more accurate reference than the internally generated
bandgap voltage or to match the full-scale reference among
a system of KAD2708C chips. One option in the latter
configuration is to use one KAD2708C's internally generated
reference as the external reference voltage for the other
chips in the system. Additionally, an externally provided
reference can be changed from the nominal value to adjust
the full-scale input voltage within a limited range.
To select whether the full-scale reference is internally
generated or externally provided, the digital input port
VREFSEL should be set appropriately, low for internal or
high for external.This pin also has an internal 18kΩ pull-up
resistor. To use the internally generated reference,
VREFSEL can be tied directly to AVSS, and to use an
external reference, VREFSEL can be left unconnected.
Analog Input
The fully differential ADC input (INP/INN) connects to the
sample and hold circuit. The ideal full-scale input voltage is
1.5VPP, centered at the VCM voltage of 0.86V as shown in
Figure 22.
V
1.8
1.4
0.75V
INP
INN
VCM
1.0
0.86V
0.6
-0.75V
0.2
t
FIGURE 22. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are
driven differentially in an ac-coupled configuration. The
common-mode output voltage, VCM, should be used to
properly bias each input as shown in Figures 23 and 24. An
RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate
frequency (IF) inputs. The recommended biasing is shown in
Figures 23 and 24.
FIGURE 21. CALIBRATION TIMING
11 FN6812.0
December 5, 2008

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