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PDF EDGE6420 Data sheet ( Hoja de datos )
| Número de pieza | EDGE6420 | |
| Descripción | Per-Pin Electronics Companion DAC | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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HIGwHw-wP.DEatRaSFheOetR4UM.coAmNCE PRODUCTS – ATE
Description
Features
Edge6420
Per-Pin Electronics
Companion DAC
The Edge6420 is a monolithic device which has 64
integrated DACs that are designed specifically for all per
channel wide-voltage and current levels needed for pin
electronics inside automatic test equipment. The chip
can also be used for other applications requiring multiple
integrated voltage or current DAC outputs.
Voltage DACs
• Wide voltage (17V range)
• Adjustable full scale range
• Adjustable minimum output
• 13 bits resolution
Current DACs
• ~3.6 mA full scale range
• Adjustable full scale range
• 6/13 bits resolution
64 Total DACs/Package Including:
• Wide Voltage Output Range (17V Range); Useful
for Supervoltage
• 44 Voltage DACs / Package
• 20 Current DACs / Package
• Adjustable Full Scale Range
• Adjustable Output Voltage Offset
• Small 13x13mm BGA Package
• All DACs are Guaranteed Monotonic
Applications
• Test Equipment
• Applications requiring multiple programmable
voltage and currents
The DACs are programmed using a serial interface.
The inclusion of 64 total DACs into 1 package offers an
extremely high density, flexible solution normally
implemented using multiple components.
Functional Block Diagram
SDI
CE
CK
UPDATE
RESET*
DAC 0
DAC 63
Channel 0
VOUT_CH0_[0:10]
IOUT_CH0_[0:4]
Channel 1
VOUT_CH1_[0:10]
IOUT_CH1[0:4]
Channel 2
VOUT_CH2_[0:10]
IOUT_CH2_[0:4]
Channel 3
VOUT_CH3_[0:10]
IOUT_CH3_[0:4]
SDO CK_OUT
Revision 4 / April 29, 2002
1
www .semtech.com
1 page  
HIGH-PERFORMANCE PRODUCTS – ATE
PINwwDwe.DsatcaSrihpeetti4oUn.co(mcontinued)
13mm x 13mm CSPBGA Package
Bottom View
Edge6420
Actual Size
A1 Ball Pad
Indicator
15 14 13 12
A15
109
A14
111
A13
113
A12
116
N/C
B15
N/C
B14
N/C
B13
N/C
B12
108 110
112 115
N/C
C15
N/C
C14
N/C
C13
N/C
C12
106 105
107 114
IOUT_CH0_0
D15
IOUT_CH0_1
D14
N/C
D13
103 102
104
AVCC
D12
VOUT_CH0_9 VOUT_CH0_8 VOUT_CH0_10
E15 E14 E13 E12
100 99
101
VOUT_CH0_6
F15
98
VOUT_CH0_5
F14
96
VOUT_CH0_7
F13
97
F12
VOUT_CH0_4
G15
95
VOUT_CH0_2
G14
93
VOUT_CH0_3
G13
94
G12
VOUT_CH0_1 IOUT_CH0_4
H15 H14
92 91
VOUT_CH0_0
H13
90
H12
IOUT_CH0_3
J15
IOUT_CH0_2
J14
89 88
IOUT_CH3_2
J13
87
J12
IOUT_CH3_3
K15
86
IOUT_CH3_4
K14
85
VOUT_CH3_0
K13
84
K12
VOUT_CH3_1 VOUT_CH3_2 VOUT_CH3_3
L15 L14 L13
83 82
81
VOUT_CH3_4
M15
VOUT_CH3_5
M14
VOUT_CH3_6
M13
80 79
78
L12
M12
VOUT_CH3_7 VOUT_CH3_8
N15 N14
VOUT_CH3_9
N13
N12
77 76
71 68
VOUT_CH3_10 IOUT_CH3_1
P15 P14
75 74
N/C
P13
69
N/C
P12
66
IOUT_CH3_0
N/C
R15 R14
73 72
N/C N/C
N/C
R13
70
N/C
N/C
R12
67
AVCC
11 10
A11
119
A10
122
CK
B11
118
CE
B10
121
SCAN_OUT
C11
SDI
C10
117 120
N/C
D11
N/C
D10
9
A9
125
VEE
B9
124
VEE
C9
123
VREF
D9
87
A8
128
A7
131
SGND
B8
127
N/C
B7
129
AGND
C8
DVDD
C7
126 130
DGND
D8
AVDD
D7
65
4
A6
134
A5
136
A4
139
CK_OUT
B6
N/C
B5
N/C
B4
132 135 138
TEST_MODE
SDO
C6 C5
N/C
C4
133 137 140
UPDATE
D6
RESET*
N/C
D5 D4
E11 E10 E9
E8 E7
E6 E5 E4
F11 F10 F9
F8 F7
F6 F5 F4
G11 G10 G9
G8 G7
G6 G5 G4
NOTE: Balls populating the inner
H11
H10
9x9
H9
grid
aHre8
for
imHp7roved
thermal
H6
H5
dissipation. This middle grid of
balls should be connected to the
VEE plane or left floating. Order
J11 J10 EJ69 420BBGJ8if popuJl7ated middJ6le J5
is desired.
H4
J4
K11 K10 K9
K8 K7
K6 K5 K4
L11 L10 L9
L8 L7
L6 L5 L4
M11
M10
M9
M8 M7
M6 M5 M4
N11
65
N/C
P11
63
R_GAIN_A
R11
64
N/C
N10
61
R_GAIN_C
P10
60
R_GAIN_D
R10
62
R_GAIN_B
N9
58
R_GAIN_F
P9
57
VEE
R9
59
R_GAIN_E
N8
54
AGND
P8
55
DGND
R8
56
VEE
N7
51
AVDD
P7
52
DVDD
R7
53
SGND
N6 N5
48 45
R_OFFSET_C
P6
49
N/C
P5
46
N4
42
AVCC
P4
43
R_OFFSET_B
R6
R_MASTER
R5
N/C
R4
50 47 44
R_OFFSET_A R_OFFSET_D
N/C
3 21
A3
142
A2
144
A1
1
N/C
B3
141
N/C
C3
143
N/C
B2
2
N/C
C2
4
N/C
B1
3
IOUT_CH1_0
C1
5
AVCC
D3
6
IOUT_CH1_1
D2
7
VOUT_CH1_10
D1
8
VOUT_CH1_9 VOUT_CH1_8 VOUT_CH1_7
E3 E2 E1
9 10 11
VOUT_CH1_6
F3
12
VOUT_CH1_5
F2
13
VOUT_CH1_4
F1
14
VOUT_CH1_3
G3
15
VOUT_CH1_2
G2
16
VOUT_CH1_1
G1
17
VOUT_CH1_0
H3
18
IOUT_CH1_4
H2
19
IOUT_CH1_3
H1
20
IOUT_CH1_2
J3
IOUT_CH2_2
J2
IOUT_CH2_3
J1
22 21
23
VOUT_CH2_0 IOUT_CH2_4
K3 K2
25 24
VOUT_CH2_1
K1
26
A
B
C
D
E
F
G
H
J
K
VOUT_CH2_3 VOUT_CH2_2 VOUT_CH2_4
L3 L2 L1
29 27
28
VOUT_CH2_7 VOUT_CH2_5 VOUT_CH2_6
M3
32
M2
30
M1
31
L
M
VOUT_CH2_10 VOUT_CH2_8
N3 N2
35 33
VOUT_CH2_9
N1
34
N/C
P3
40
IOUT_CH2_1
P2
38
IOUT_CH2_0
P1
36
N/C
R3
41
N/C
N/C
R2
39
N/C
N/C
R1
37
N/C
N
P
R
2000 Semtech Corp.
5 www .semtech.com
5 Page 
HIGH-PERFORMANCE PRODUCTS – ATE
Circwuwwit.DDataeSshecert4ipU.tcioomn (continued)
RESET*
Decode and Individual DAC Update
This is a 13-bit latch for DAC
(Note: there are some current output
DACs that require only 6-bit latches)
LQ
EN R
LQ
EN R
.
.
.
ADDRESS
DECODER
ADDR
7
LQ
EN R
13
UPDATE
CE
CK
SDI
RESET*
Delay
DQ
R
LOAD
CENTRAL DAC LATCH
(24 Latches)
RESET
24-BIT SHIFT REGISTER
RESET
Programming Logic
Figure 1. DAC Functionality Block Diagram
2000 Semtech Corp.
11
Edge6420
DAC DAC output #0
DAC DAC output #1
.
.
.
DAC DAC output #63
CK_OUT
SDO
www .semtech.com
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet EDGE6420.PDF ] | |
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