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PDF A6282 Data sheet ( Hoja de datos )
| Número de pieza | A6282 | |
| Descripción | 16-Channel Constant-Current LED Driver | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A6282
16-Channel Constant-Current LEDDriver
Features and Benefits
▪ 16 constant-current outputs, up to 50 mA each
▪ LED output voltage up to 12 V
▪ 3.0 to 5.5 V logic supply range
▪ Schmitt trigger inputs for improved noise immunity
▪ Power-On Reset (POR), all register bits = 0
▪ Low-power CMOS logic and latches
▪ High data input rate: 30 MHz
▪ Output current accuracy: between channels < ±3% and
between ICs ±7%, over the full operating temperature
range
▪ Internal UVLO and thermal shutdown (TSD) circuitry
Packages:
24-pin TSSOP
with exposed thermal pad
(Package LP)
Not to scale
24-contact QFN
4 mm × 4 mm × 0.75 mm
(Package ES)
Description
TheA6282 device is designed for LED display applications.This
CMOS device includes an input shift register, accompanying
data latches, and 16 MOS constant current sink drivers.
The CMOS shift registers and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data input rates can reach up to 30 MHz.
The LED drive current level can be set by a single external
resistor, selected by the application designer. A serial data
output permits cascading of multiple devices in applications
requiring additional drive lines.
The A6282 is available in two 24-terminal packages: QFN
(package ES) and TSSOP (LP), which have an exposed
thermal pad. Both packages are lead (Pb) free with 100% matte
tin leadframe plating.
Applications include the following:
▪ Monocolor, multicolor, or full-color LED display
▪ Monocolor, multicolor, or full-color LED signboard
▪ Display backlighting
▪ Multicolor LED lighting
SDI
Controller
CLK
LE
OE
Typical Application
VLED
10 μF
SDI OUT0
OUT15
SDO
CLK VDD VDD
LE A6282
100 nF
GND
OE
REXT
IC 1
SDI
CLK
LE
OE
10 μF
OUT0
A6282
OUT15 SDO
VDD VDD
100 nF
GND
REXT
IC 2
6282-DS, Rev. 4
Cascaded A6282 devices
1 page  
A6282
16-Channel Constant-Current LED Driver
ELECTRICAL CHARACTERISTICS at TA1 = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
Characteristic
Symbol
Test Conditions
Min.
Logic Supply Voltage Range
LED Load Supply Output Voltage
Undervoltage Lockout
Output Current
Output Current Shift
VDD
VLED
VDD(UV)
IO
%∆IO
Operating
Operating
VDD 0 → 5.0 V
VDD 5 → 0.0 V
VDD = 4.5 to 5.5 V, VDS(x) = 1 V,
REXT = 374
VDD = 3.0 to 3.6 V, VDS(x) = 1 V,
REXT = 374
VDD = 4.5 to 5.5 V, VDS(x) = 1 V,
REXT = 910
VDD = 3.0 to 3.6 V, VDS(x) = 1 V,
REXT = 910
VDD = 5.5 V, VDS(x) = 1 V, REXT = 910 Ω,
TA = 25°C; between one output on and
all outputs on
3.0
–
2.5
2.3
47.4
46.5
19.8
19.5
–
Output to Output Matching Error3
Output Current Regulation
Output Leakage Current
Logic Input Voltage
Logic Input Voltage Hysteresis
Logic Input Current
SDO Voltage
Supply Current4
Err
%IO(reg)
IDSS
VIH
VIL
VIhys
II
VOL
VOH
IDD(OFF)
IDD(ON)
VDS = 1 V, REXT = 374 , all outputs on
VDS = 1 V, REXT = 910 , all outputs on
VDD = 5.5 V, VDS(x) = 1 to 3 V,
REXT = 374 , all outputs on
VDD = 5.5 V, VDS(x) = 1 to 3 V,
REXT = 910 , all outputs on
VDD = 3.6 V, VDS(x) = 1 to 3 V,
REXT = 374 , all outputs on
VDD = 3.6 V, VDS(x) = 1 to 3 V,
REXT = 910 , all outputs on
VOH = 12 V
All digital inputs
All digital inputs
IOL = 1 mA
IOH = –1 mA
REXT = 3.8 k, VOE = 5 V
REXT = 910 , VOE = 5 V
REXT = 374 , VOE = 5 V
All outputs on, REXT = 910 , VO = 1 V,
data transfer 30 MHz
All outputs on, REXT = 374 , VO = 1 V,
data transfer 30 MHz
–
–
–
–
–
–
–
0.8×VDD
GND
250
–1
–
VDD – 0.5
–
–
–
–
–
Typ.2
5.0
–
2.7
2.5
51.1
50.1
21.4
21.0
–
+1.0
+1.0
1.7
2.4
1.2
1.8
–
–
–
–
–
–
–
–
–
–
–
–
Max.
5.5
12.0
2.9
2.7
54.5
53.5
22.8
22.4
±1
+3.0
+3.0
3
4
2
3
0.5
VDD
0.2×VDD
900
1
0.5
–
6
16
40
20
45
Unit
V
V
V
V
mA
mA
mA
mA
%
%
%
%/V
%/V
%/V
%/V
μA
V
V
mV
μA
V
V
mA
mA
mA
mA
mA
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page 
A6282
16-Channel Constant-Current LED Driver
Package ES, 4 mm x 4 mm, 24-pin QFN with Exposed Thermal Pad
4.00 ±0.15
24
1
2
A
4.00 ±0.15
24
0.90
1
2
0.30
0.50
2.10 4.10
25X D
0.08 C
0.25
+0.05
–0.07
0.50
SEATING C
PLANE
0.75 ±0.05
0.40
+0.15
–0.10
B
2
1
24
2.10
2.10
2.10
4.10
C PCB Layout Reference View
For Reference Only
(reference JEDEC MO-220WGGD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P400X400X80-25W6M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet A6282.PDF ] | |
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