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PDF DAC2904 Data sheet ( Hoja de datos )
| Número de pieza | DAC2904 | |
| Descripción | 125MSPS DIGITAL-TO-ANALOG CONVERTER | |
| Fabricantes | Burr-Brown | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DAC2904 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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DAC2904
DAC2904
SBAS198B – NOVEMBER 2003
Dual, 14-Bit, 125MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q 125MSPS UPDATE RATE
q SINGLE SUPPLY: +3.3V or +5V
www.DataSheet4U.cqomHIGH SFDR: 78dB at fOUT = 10MHz
q LOW GLITCH: 2pVs
q LOW POWER: 310mW
q INTERNAL REFERENCE
q POWER-DOWN MODE: 23mW
DESCRIPTION
The DAC2904 is a monolithic, 14-bit, dual-channel,
high-speed Digital-to-Analog Converter (DAC), and is opti-
mized to provide high dynamic performance while dissipating
only 310mW.
Operating with high update rates of up to 125MSPS, the
DAC2904 offers exceptional dynamic performance, and
enables the generation of very-high output frequencies suit-
able for “Direct IF” applications. The DAC2904 has been
optimized for communications applications in which sepa-
rate I and Q data are processed while maintaining tight-gain
and offset matching.
Each DAC has a high-impedance differential-current output,
suitable for single-ended or differential analog-output con-
figurations.
APPLICATIONS
q COMMUNICATIONS:
Base Stations, WLL, WLAN
Baseband I/Q Modulation
q MEDICAL/TEST INSTRUMENTATION
q ARBITRARY WAVEFORM GENERATORS (ARB)
q DIRECT DIGITAL SYNTHESIS (DDS)
The DAC2904 combines high dynamic performance with a
high update rate to create a cost-effective solution for a wide
variety of waveform-synthesis applications:
• Pin compatibility between family members provides 10-bit
(DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904)
resolution.
• Pin compatible to the AD9767 dual DAC.
• Gain matching is typically 0.5% of full-scale, and offset
matching is specified at 0.02% max.
• The DAC2904 utilizes an advanced CMOS process; the
segmented architecture minimizes output-glitch energy,
and maximizes the dynamic performance.
• All digital inputs are +3.3V and +5V logic compatible. The
DAC2904 has an internal reference circuit, and allows use
in a multiplying configuration.
• The DAC2904 is available in a TQFP-48 package, and is
specified over the extended industrial temperature range of
–40°C to +85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2002-2003, Texas Instruments
Incorporated
1 page  
TIMING DIAGRAM
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DATA IN
WRT1
WRT2
CLK1
CLK2
IOUT1
IOUT2
tS tH
D[13:0](n)
tLPW
tCPW
D[13:0](n + 1)
50%
tSET
IOUT(n)
tPD
IOUT(n + 1)
SYMBOL
tS
tH
tLPW, tCPW
tCW
tPD
tSET
DESCRIPTION
MIN
TYP
MAX
UNITS
Input Setup Time
Input Hold Time
Latch/Clock Pulsewidth
Delay Rising CLK Edge to
Rising WRT Edge
Propagation Delay
Settling Time (0.1%)
2
1.5
3.5
0
ns
ns
4 ns
tPW – 2
ns
1 ns
30 ns
DIGITAL INPUTS AND TIMING
The data input ports of the DAC2904 accepts a standard
positive coding with data bit D13 being the most significant
bit (MSB). The converter outputs support a clock rate of up
to 125MSPS. The best performance will typically be achieved
with a symmetric duty cycle for write and clock; however,
the duty cycle may vary as long as the timing specifications
are met. Also, the set-up and hold times may be chosen
within their specified limits.
All digital inputs of the DAC2904 are CMOS compatible.
The logic thresholds depend on the applied digital supply
voltages, such that they are set to approximately half the
supply voltage; Vth = +VD/2 (±20% tolerance). The DAC2904
is designed to operate with a digital supply (+VD) of +3.0V
to +5.5V.
The two converter channels within the DAC2904 consist of
two independent, 14-bit, parallel data ports. Each DAC-
channel is controlled by its own set of write (WRT1, WRT2)
and clock (CLK1, CLK2) inputs. Here, the WRT lines
control the channel input latches and the CLK lines control
the DAC latches. The data is first loaded into the input latch
by a rising edge of the WRT line. This data is presented to
the DAC latch on the following falling edge of the WRT
signal. On the next rising edge of the CLK line, the DAC is
updated with the new data and the analog output signal will
change accordingly. The double latch architecture of the
DAC2904 results in a defined sequence for the WRT and
CLK signals, expressed by parameter ‘tCW’. A correct tim-
ing is observed when the rising edge of CLK occurs at the
same time, or before, the rising edge of the WRT signal. This
condition can simply be met by connecting the WRT and
CLK lines together. Note that all specifications were mea-
sured with the WRT and CLK lines connected together.
DAC2904
SBAS198B
5
5 Page 
As shown in Figure 3, the transformer’s center tap is con-
nected to ground. This forces the voltage swing on IOUT and
IOUT to be centered at 0V. In this case the two resistors, RL,
may be replaced with one, RDIFF, or omitted altogether. This
approach should only be used if all components are close to
each other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can be
realized, but the output compliance range should be ob-
served. Alternatively, if the center tap is not connected, the
signal swing will be centered at RL • IOUTFS/2. However, in
this case, the two resistors, RL, must be used to enable the
necessary DC-current flow for both outputs.
www.DataSheet4U.com
IOUT
DAC2904
IOUT
RDIFF
100Ω
RL
50Ω
ADTT1-1
(Mini-Circuits)
1:1
RL
50Ω
RS
50Ω
FIGURE 3. Differential Output Configuration Using an RF
Transformer.
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a DC-coupled output, a difference
amplifier may be considered, as shown in Figure 4. Four
external resistors are needed to configure the voltage-feed-
back op amp OPA680 as a difference amplifier performing
the differential to single-ended conversion. Under the shown
configuration, the DAC2904 generates a differential output
signal of 0.5Vp-p at the load resistors, RL. The resistor
values shown were selected to result in a symmetric 25Ω
loading for each of the current outputs since the input
impedance of the difference amplifier is in parallel to resis-
tors RL, and should be considered.
IOUT
DAC2904
IOUT
R1
200Ω
COPT
RL
26.1Ω
R3
200Ω
RL
28.7Ω
R2
402Ω
OPA680
–5V +5V
R4
402Ω
VOUT
FIGURE 4. Difference Amplifier Provides Differential to
Single-Ended Conversion and DC-Coupling.
The OPA680 is configured for a gain of two. Therefore,
operating the DAC2904 with a 20mA full-scale output will
produce a voltage output of ±1V. This requires the amplifier
to operate off of a dual power supply (±5V). The tolerance
of the resistors typically sets the limit for the achievable
common-mode rejection. An improvement can be obtained
by fine tuning resistor R4.
This configuration typically delivers a lower level of AC
performance than the previously discussed transformer solu-
tion because the amplifier introduces another source of
distortion. Suitable amplifiers should be selected based on
their slew-rate, harmonic distortion, and output swing capa-
bilities. High-speed amplifiers like the OPA680 or OPA687
may be considered. The AC performance of this circuit may
be improved by adding a small capacitor, CDIFF, between the
outputs IOUT and IOUT (see Figure 4). This will introduce a
real pole to create a low-pass filter in order to slew-limit the
DAC’s fast output signal steps, which otherwise could drive
the amplifier into slew-limitations or into an overload con-
dition; both would cause excessive distortion. The differ-
ence amplifier can easily be modified to add a level shift for
applications requiring the single-ended output voltage to be
unipolar, i.e., swing between 0V and +2V.
DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION
The circuit example of Figure 5 shows the signal output
currents connected into the summing junctions of the dual
voltage-feedback op amp OPA2680 that is set up as a
transimpedance stage, or ‘I-to-V converter’. With this cir-
cuit, the DAC’s output will be kept at a virtual ground,
minimizing the effects of output impedance variations, which
results in the best DC linearity (INL). As mentioned previ-
ously, care should be taken not to drive the amplifier into
slew-rate limitations, and produce unwanted distortion.
+5V
50Ω
1/2
OPA2680
DAC2904
IOUT
CD1
IOUT
CD2
RF1
CF1
RF2
CF2
–VOUT = IOUT • RF1
1/2
OPA2680
50Ω
–5V
–VOUT = IOUT • RF2
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680
Forms Differential Transimpedance Amplifier.
DAC2904
SBAS198B
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet DAC2904.PDF ] | |
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