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PDF M11B16161A Data sheet ( Hoja de datos )
| Número de pieza | M11B16161A | |
| Descripción | (M11x16161xA) 1M X 16 DRAM | |
| Fabricantes | EliteMT | |
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DRAM
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
1M x 16 DRAM
EDO PAGE MODE
FEATURES
ORDERING INFORMATION - PACKAGE
y X16 organization
y EDO (Extended Data-Out) access mode
y 2 CAS Byte/Word Read/Write operation
y Single power supply :
5V ± 10% Vcc for 5V product
www.DataSheet43U.3.cVom± 10% Vcc for 3.3V product
y Interface for inputs and outputs
TTL-compatible for 5V products
LVTTL-compatible for 3.3V products
y 1024-cycle refresh in 16ms
y Refresh modes : RAS only, CAS BEFORE RAS (CBR)
and HIDDEN capabilities,
y Optional self-Refresh capabilities(S-ver. Only)
y JEDEC standard pinout
y Key AC Parameter
tRAC
tCAC
tRC
tPC
-45 45 11 77 16
-50 50 13 84 20
-60 60
15 104 25
42-pin 400mil SOJ
44 / 50-pin 400mil TSOP (TypeII)
PRODUCT NO.
Refresh
Vcc
PACKING
TYPE
M11B16161A-45J/50J/60J Normal
M11B16161SA-45J/50J/60J
*Self-
Refresh
5V
M11L16161A-45J/50J/60J Normal
M11L16161SA-45J/50J/60J
Self- 3.3V
Refresh
M11B16161A-45T/50T/60T Normal
M11B16161SA-45T/50T/60T
*Self-
Refresh
5V
M11L16161A-45T/50T/60T Normal
M11L16161SA-45T/50T/60T
Self-
Refresh
3.3V
* Ordered by special request
SOJ
TSOPII
GENERAL DESCRIPTION
The M11B16161/M11L16161 series is a randomly accessed solid state memory, organized as 1,048,576 x 16 bits device. It
offers Extended Data-Output access mode. Single power supply (5V ± 10%, 3.3V ± 10%), access time (-45,-50,-60), self-
refresh function and package type (SOJ, TSOP II) are optional features of this family. All these family have CAS - before -
RAS , RAS -only refresh and Hidden refresh.
Two access modes are supported by this device : Byte access and Word access. Use only one of the two CAS and leave
the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used. CASL
transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH transiting low will
output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 VSS
41 I/O15
40 I/O14
39 I/O13
38 I/O12
37 VSS
36 I/O11
35 I/O10
34 I/O9
33 I/O8
32 N C
31 CASL
30 CASH
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 VSS
TSOP (TypeII) Top View
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
4 4 VSS
4 3 I/O15
4 2 I/O14
4 1 I/O13
4 0 I/O12
3 9 VSS
3 8 I/O11
3 7 I/O10
3 6 I/O9
3 5 I/O8
34 NC
33 NC
3 2 CASL
3 1 CASH
3 0 OE
2 9 A9
2 8 A8
2 7 A7
2 6 A6
2 5 A5
2 4 A4
2 3 VSS
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.3
1/16
1 page  
$ %
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
(Continued)
PARAMETER
-45
SYMBOL
MIN MAX
Read Command Setup Time
Read Command Hold Time Reference to CAS
tRCS
tRCH
0
0
Read Command Hold Time Reference to RAS
tRRH
0
CAS to Output in Low-Z
tCLZ 0
Output Buffer Turn-off Delay From CAS or RAS
tOFF1
0 11
Output Buffer Turn-off to OE
www.DataSheWet4riUte.cComommand Setup Time
Write Command Hold Time
Write Command Hold Time(Reference to RAS )
Write Command Pulse Width
Write Command to RAS Lead Time
tOFF2
tWCS
tWCH
tWCR
tWP
tRWL
0 11
0
6
40
6
11
Write Command to CAS Lead Time
Data-in Setup Time
Data-in Hold Time
Data-in Hold Time (Reference to RAS )
tCWL
tDS
tDH
tDHR
6
0
6
40
RAS to WE Delay Time
tRWD
57
Column Address to WE Delay Time
tAWD
34
CAS to WE Delay Time
Transition Time (rise or fall)
Refresh Period (1024 cycles)
Refresh Period (1024 cycles) Self Refresh
RAS to CAS Precharge Time
tCWD
tT
tREF
tREF
tRPC
23
1 50
16
64
5
CAS Setup Time(CBR REFRESH)
tCSR
5
CAS Hold Time(CBR REFRESH)
tCHR
10
OE Hold Time From WE During Read-Mode-Write
Cycle
OE Low to CAS High Setup Time
tOEH
tOES
6
5
OE High Hold Time From CAS High
tOEHC
2
OE Precharge Time
tOEP
2
OE Setup Prior to RAS During Hidden Refresh
Cycle
tORD
0
-50
MIN MAX
0
0
0
0
0 13
0 13
0
7
44
7
13
7
0
7
44
67
42
30
1 50
16
64
5
5
10
7
5
2
2
0
-60 UNIT Notes
MIN MAX
0 ns 15,18
0 ns 9,15,19
0 ns 9
0 ns 20
0 15 ns 10,17,20
0 15 ns 17,26
0 ns 11,15,18
10 ns 15,25
55 ns 15
10 ns 15
15 ns 15
10 ns 15,19
0 ns 12,20
10 ns 12,20
55 ns
79 ns 11
49 ns 11
34 ns 11,18
1 50 ns
16 ms
64 ms
2,3
5 ns
5 ns 1,18
10 ns 1,19
10 ns 16
5 ns
2 ns
2 ns
0 ns
Last CAS Going Low to First CAS Returning High tCLCH
6
7 10 ns 21
Data Output Hold After CAS Returning Low
Output Disable Delay From WE
Self Refresh RAS Low Pulse width
Self Refresh RAS High Precharge Time
Self Refresh CAS Hold Time
Read Setup Time Reference to RAS in CBR/SR
Read Hold Time Reference to RAS in CBR/SR
tCOH
3
3
3 ns
tWHZ 0 11 0 13 0 15 ns
tRASS 100 100 100
us 27,28
tRPS
77
84 104 ns 27,28
tCHS
-50
-50 -50
ns 27,28
tRSR
0
0
0 ns 27,28
tRHR
6
7 10 ns 27,28
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.3
5/16
5 Page 
$ %
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
www.DataSheet4U.com
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Psuedo READ-MODIFY-WRITE)
RAS
VIH
VIL
VIH
CASL,CASH VIL
VIH
ADDR VIL
VIH
W E VIL
VI/OH
I/O VI/OL
VIH
OE VIL
tRASC
tCRP
t RC D
tCSH
tPC
tC AS
tCP
tCP
t CAS
tCP
tRSH
t CAS
tRAD
tASR tRAH
tAR
tASC
tCAH
ROW
COLUMN(A)
tRCS
tASC tCAH
COLUMN(B)
tRCH
tASC
tRAL
tACH
t CAH
CO L U MN ( N)
tW CS
tWCH
tAA
tRAC
tCAC
OPEN
tOAC
t ACP
tAA
t CAC
tCOH
tW HZ
VALID DATA(A)
VAL I D
DA TA( B )
tDS tDH
VALID
DATA IN
tRP
tCP
ROW
RAS
VIH
VIL
VIH
CASL,CASH VIL
VIH
ADDR VIL
VO H
I/O VOL
RAS ONLY REFRESH CYCLE
(ADDR = A0~A9 ; OE , WE = DON’T CARE)
tC RP
tASR
t RAH
ROW
t RAS
tRC
OPEN
tRP
tRPC
ROW
DON'T CARE
UNDEFINED
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.3
11/16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet M11B16161A.PDF ] | |
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