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PDF M11B1644A Data sheet ( Hoja de datos )

Número de pieza M11B1644A
Descripción (M11x1644xA) 4M X 4 DRAM
Fabricantes EliteMT 
Logotipo EliteMT Logotipo



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No Preview Available ! M11B1644A Hoja de datos, Descripción, Manual

$%
DRAM
M11B1644A / M11B1644SA
M11L1644A / M11L1644SA
4M x 4 DRAM
EDO PAGE MODE
FEATURES
ORDERING INFORMATION - PACKAGE
y X4 organization
y EDO (Extended Data-Out) access mode
y Single power supply :
5V ± 10% Vcc for 5V product
3.3V ± 10% Vcc for 3.3V product
www.DataShyeetI4nUte.crofamce for inputs and outputs
TTL-compatible for 5V products
LVTTL-compatible for 3.3V products
y 2048-cycle refresh in 32ms
y Refresh modes : RAS only, CAS BEFORE RAS (CBR)
and HIDDEN capabilities,
y Optional self-Refresh capabilities(S-ver. Only)
y JEDEC standard pinout
y Key AC Parameter
tRAC
tCAC
tRC
tPC
-45 45 11 77 16
-50 50 13 84 20
-60 60
15 104 25
GENERAL DESCRIPTION
24 / 26-pin 300mil SOJ
24 / 26-pin 300mil TSOP (TypeII)
PRODUCT NO.
Refresh
Vcc
PACKING
TYPE
M11B1644A-45J/50J/60J
M11B1644SA-45J/50J/60J
Normal
*Self- 5V
Refresh
M11L1644A-45J/50J/60J
M11L1644SA-45J/50J/60J
Normal
Self- 3.3V
Refresh
M11B1644A-45T/50T/60T Normal
M11B1644SA-45T/50T/60T
*Self-
Refresh
5V
M11L1644A-45T/50T/60T
M11L1644SA-45T/50T/60T
Normal
Self- 3.3V
Refresh
* Ordered by special request
SOJ
TSOPII
The M11B1644/M11L1644 series is a randomly accessed solid state memory, organized as 4,194,304 x 4 bits device. It
offers Extended Data-Output access mode. Single power supply (5V ± 10%, 3.3V ± 10%), access time (-45,-50,-60), self-
refresh function and package type (SOJ, TSOP II) are optional features of this family. All these family have CAS - before -
RAS , RAS -only refresh and Hidden refresh.
The primary advantage of EDO is the availability of data-out even after CAS returns high. EDO allows CAS precharge
time (tPC) to occur without the output data going invalid. This elimination of CAS output control allows pipeline Read.
PIN ASSIGNMENT
SOJ Top View
VCC
I/O0
I/O1
WE
RAS
NC
1
2
3
4
5
6
2 4 VSS
2 3 I/O3
22 I/O2
2 1 CAS
2 0 OE
1 9 A9
A10 7
A0 8
A1 9
A2 1 0
A3 1 1
VCC 1 2
1 8 A8
1 7 A7
1 6 A6
1 5 A5
1 4 A4
1 3 VSS
TSOP (TypeII) Top View
VCC
I/O 0
I/O 1
WE
RAS
NC
1
2
3
4
5
6
2 4 VSS
2 3 I/O3
22 I/O2
2 1 CAS
2 0 OE
1 9 A9
A10 7
A0 8
A1 9
A2 1 0
A3 1 1
VCC 1 2
1 8 A8
1 7 A7
1 6 A6
1 5 A5
1 4 A4
1 3 VSS
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.1
1/16

1 page




M11B1644A pdf
$%
M11B1644A / M11B1644SA
M11L1644A / M11L1644SA
(Continued)
PARAMETER
-45
SYMBOL
MIN MAX
Read Command Setup Time
Read Command Hold Time Reference to CAS
tRCS
tRCH
0
0
Read Command Hold Time Reference to RAS
tRRH
0
CAS to Output in Low-Z
tCLZ 0
Output Buffer Turn-off Delay From CAS or RAS
tOFF1
0 11
Output Buffer Turn-off to OE
www.DataSheWet4riUte.cComommand Setup Time
Write Command Hold Time
Write Command Hold Time(Reference to RAS )
Write Command Pulse Width
Write Command to RAS Lead Time
tOFF2
tWCS
tWCH
tWCR
tWP
tRWL
0 11
0
6
40
6
11
Write Command to CAS Lead Time
Data-in Setup Time
Data-in Hold Time
Data-in Hold Time (Reference to RAS )
tCWL
tDS
tDH
tDHR
6
0
6
40
RAS to WE Delay Time
tRWD
57
Column Address to WE Delay Time
tAWD
34
CAS to WE Delay Time
Transition Time (rise or fall)
Refresh Period (2048 cycles)
RAS to CAS Precharge Time
tCWD
tT
tREF
tRPC
23
1 50
32
5
CAS Setup Time(CBR REFRESH)
tCSR
5
CAS Hold Time(CBR REFRESH)
tCHR
10
OE Hold Time From WE During Read-Mode-Write
Cycle
OE Low to CAS High Setup Time
tOEH
tOES
6
5
OE High Hold Time From CAS High
tOEHC
2
OE precharge time
tOEP
2
OE Setup Prior to RAS During Hidden Refresh
Cycle
Data Output Hold After CAS Returning Low
tORD
tCOH
0
3
Output Disable Delay From WE
Self Refresh RAS Low Pulse width
tWHZ
tRASS
0 11
100
Self Refresh RAS High Precharge Time
tRPS
77
Self Refresh CAS Hold Time
tCHS
-50
WE Setup Time Reference to RAS in CBR/SR
tRSR
0
WE Hold Time Reference to RAS in CBR/SR
tRHR
6
-50
MIN MAX
0
0
0
0
0 13
0 13
0
7
44
7
13
7
0
7
44
67
42
30
1 50
32
5
5
10
7
5
2
2
0
3
0 13
100
84
-50
0
7
-60 UNIT
MIN MAX
0 ns
0 ns
0 ns
0 ns
0 15 ns
0 15 ns
0 ns
10 ns
55 ns
10 ns
15 ns
10 ns
0 ns
10 ns
55 ns
79 ns
49 ns
34 ns
1 50 ns
32 ms
5 ns
5 ns
10 ns
10 ns
5 ns
2 ns
2 ns
0 ns
3
0 15
100
104
-50
0
10
ns
ns
us
ns
ns
ns
ns
Notes
15
9,15
9
10,17
17,19
11,15
15
15
15
15
15
12
12
11
11
11
2,3
1
1
16
20,21
20,21
20,21
20,21
20,21
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.1
5/16

5 Page





M11B1644A arduino
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M11B1644A / M11B1644SA
M11L1644A / M11L1644SA
www.DataSheet4U.com
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Psuedo READ-MODIFY-WRITE)
V IH
RAS VIL
CAS
V IH
V IL
VIH
ADDR VIL
VIH
WE VIL
VI/O H
I/ O VI /O L
VIH
OE VIL
t RASC
tC RP
tRCD
tC SH
tPC
tCAS
tCP
tCP
tCAS
tCP
tR SH
tCAS
t RAD
tAS R tR AH
tAR
tASC
tACH
tC AH
ROW
COLUMN(A)
tRCS
t ASC
tACH
tCAH
COLUMN(B)
t RC H
tASC
tRAL
tACH
tCAH
COLUMN(N)
tWCS
t WCH
tAA
tRAC
t CAC
OPEN
t O AC
tACP
tAA
tCAC
tCOH
tW HZ
VALID DATA(A)
VA LI D
D ATA (B )
tDS tDH
VALID
DATA IN
tRP
tCP
ROW
VIH
RAS VIL
CAS
VIH
VIL
VIH
ADDR VIL
VOH
I/O VOL
RAS ONLY REFRESH CYCLE
(ADDR = A0~A10 ; OE , WE = DON’T CARE)
tCRP
t AS R
tRAH
ROW
tRAS
tR C
OPEN
tRP
tRPC
ROW
DON'T CARE
UNDEFINED
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.1
11/16

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