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PDF K4D26323QG Data sheet ( Hoja de datos )
| Número de pieza | K4D26323QG | |
| Descripción | 128Mbit GDDR SDRAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K4D26323QG-GC
128M GDDR SDRAM
128Mbit GDDR SDRAMwww.DataSheet4U.com
Revision 1.2
March 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev 1.2(Mar. 2005)
1 page  
K4D26323QG-GC
128M GDDR SDRAM
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ’s and DM’s that are sampled on both edges of the DQS.
www.DataSheet4U.com CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQS0 ~ DQS3
Input/Output
Data input and output are synchronized with both edge of DQS.
DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23,
DQS3 for DQ24 ~ DQ31.
DM0 ~ DM3
Input
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for
DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
DQ0 ~ DQ31
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA0, BA1
Input
Selects which bank is to be active.
A0 ~ A11
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7.
Column address CA8 is used for auto precharge.
VDD/VSS
Power Supply
Power and ground for the input buffers and core logic.
VDDQ/VSSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VREF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
This pin is recommended to be left "No connection" on the device
Reserved for future use
MCL
Must Connect Low
Must connect low
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
-5-
Rev 1.2(Mar. 2005)
5 Page 
K4D26323QG-GC
128M GDDR SDRAM
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)
Parameter
Symbol
Test Condition
Operating Current
(One Bank Active)
ICC1
Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
Precharge Standby Current
www.DataSheeti4nUP.coowmer-down mode
ICC2P
CKE ≤ VIL(max), tCC= tCC(min)
Precharge Standby Current
in Non Power-down mode
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
Active Standby Current
power-down mode
ICC3P
CKE ≤ VIL(max), tCC= tCC(min)
Active Standby Current
in Non Power-down mode
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
Operating Current
( Burst Mode)
ICC4
IOL=0mA ,tCC= tCC(min),
Page Burst, All Banks activated.
Refresh Current
ICC5
tRC ≥ tRFC(min)
Self Refresh Current
ICC6
CKE ≤ 0.2V
Operating Current
(4Bank interleaving)
ICC7
Burst Length=4 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
Note : 1. Measured with output open
2. Refresh period is 32ms
3. Current meassured at VDD(max)
-25
260
10
65
65
210
475
265
570
Version
-2A
230
10
60
60
190
440
240
8
520
Unit Note
-33
220 mA
10 mA
50 mA
50 mA
170 mA
410 mA
225 mA 1
mA
460 mA
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter
Input High (Logic 1) Voltage ;DQ
Input Low (Logic 0) Voltage; DQ
Clock Input Differential Voltage; CK and CK
Symbol
VIH
VIL
VID
Min
VREF+0.35
-
0.7
Typ
-
-
-
Max
-
VREF-0.35
VDDQ+0.6
Unit
V
V
V
Note
1
Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2
-
0.5*VDDQ+0.2
V
2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
- 11 -
Rev 1.2(Mar. 2005)
11 Page | ||
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