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PDF 5C6408-20 Data sheet ( Hoja de datos )

Número de pieza 5C6408-20
Descripción MT5C6408
Fabricantes Austin Semiconductor 
Logotipo Austin Semiconductor Logotipo



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No Preview Available ! 5C6408-20 Hoja de datos, Descripción, Manual

Austin Semiconductor, Inc.
SRAM
MT5C6408
8K x 8 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-38294
• MIL-STD-883
www.DataSheeFt4EU.cAoTmURES
• High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns
• Battery Backup: 2V data retention
• High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE1\ and CE2
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-12
-15
-20
-25
-35
-45
-55*
-70*
• Package(s)
Ceramic DIP (300 mil)
Ceramic LCC
Ceramic Flatpack
C No. 108
EC No. 204
F No. 302
• Operating Temperature Ranges
Industrial (-40oC to +85oC)
IT
Military (-55oC to +125oC)
XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
28-Pin DIP (C)
(300 MIL)
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 Vcc
27 WE\
26 CE2
25 A8
24 A9
23 A11
22 OE\
21 A10
20 CE1\
19 DQ8
18 DQ7
17 DQ6
16 DQ5
15 DQ4
28-Pin LCC (EC)
4 3 2 1 28 27 26
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ0 1 1
25 A8
24 A9
23 A11
2 2 OE\
21 A10
2 0 CE1\
1 9 DQ7
12 13 14 15 16 17 18
28-Pin Flat Pack (F)
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
Vcc
WE\
CE2
A8
A9
A11
OE\
A10
CE1\
DQ8
DQ7
DQ6
DQ5
DQ4
GENERAL DESCRIPTION
The MT5C6408, 8K x 8 SRAM, employs high-speed,
low-power CMOS technology, eliminating the need for clocks
or refreshing. These SRAM’s have equal access and cycle
times.
For flexibility in high-speed memory applications,
Austin Semiconductor offers dual chip enables (CE1\, CE2) and
output enable (OE\) capability. These enhancements can place
the outputs in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.
Reading is accomplished when WE\ and CE2 remain HIGH and
CE1\ and OE\ go LOW. The device offers a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
These devices operate from a single +5V power sup-
ply and all inputs and outputs are fully TTL compatible.
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1

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5C6408-20 pdf
Austin Semiconductor, Inc.
SRAM
MT5C6408
ACTEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
167
167
Q 30pF VTH = 1.73V Q 5pF VTH = 1.73V
www.DataSheet4U.com
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than tLZWE and
tHZOE is less than tLZOE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. CE2 timing is the same as CE1\ timing. The waveform is
inverted.
13. Chip enable (CE1\, CE2) and write enable (WE\) can
initiate and terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYM MIN MAX UNITS NOTES
VCC for Retention Data
VDR
2
---
V
Data Retention Current
CE\ > (VCC - 0.2V)
VIN > (VCC - 0.2V)
or < 0.2V
VCC = 2V ICCDR
300 µA
Chip Deselect to Data
Retention Time
tCDR
0
---
ns
4
Operation Recovery Time
tR tRC
ns 4, 11
LOW Vcc DATA RETENTION WAVEFORM
MT5C6408
Rev. 3.0 2/01
VCC
tCDR
CE\
VIH
VIL
111122223333444455556666777788889999
DATA RETENTION MODE
4.5V
VDR > 2V
4.5V
VDR
tR
111122223333444455556666111177772111122288883222233343343344
111122223333DON’T CARE
1111222233334444UNDEFINED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5

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5C6408-20 arduino
Austin Semiconductor, Inc.
ORDERING INFORMATION
SRAM
MT5C6408
EXAMPLE: MT5C6408C-25L/XT
Device Number
www.DataSheet4U.com
Package
Type
Speed
ns
Options**
Process
MT5C6408
C -12 L
/*
MT5C6408
C -15 L
/*
MT5C6408
C -20 L
/*
MT5C6408
C -25 L
/*
MT5C6408
C -35 L
/*
MT5C6408
C -45 L
/*
MT5C6408
C -55 L
/*
MT5C6408
C -70 L
/*
EXAMPLE: MT5C6408F-55/883C
Device Number
Package
Type
Speed
ns
Options**
Process
MT5C6408
F -12 L
/*
MT5C6408
F -15 L
/*
MT5C6408
F -20 L
/*
MT5C6408
F -25 L
/*
MT5C6408
F -35 L
/*
MT5C6408
F -45 L
/*
MT5C6408
F -55 L
/*
MT5C6408
F -70 L
/*
EXAMPLE: MT5C6408EC-15L/IT
Device Number
Package
Type
Speed
ns
Options**
Process
MT5C6408
EC -12
L
/*
MT5C6408
EC -15
L
/*
MT5C6408
EC -20
L
/*
MT5C6408
EC -25
L
/*
MT5C6408
EC -35
L
/*
MT5C6408
EC -45
L
/*
MT5C6408
EC -55
L
/*
MT5C6408
EC -70
L
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
** OPTIONS
L = 2V Data Retention/Low Power
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
MT5C6408
Rev. 3.0 2/01
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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