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PDF R8A66151SP Data sheet ( Hoja de datos )
| Número de pieza | R8A66151SP | |
| Descripción | 24-BIT I/O EXPANDER | |
| Fabricantes | Renesas Technology | |
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R8A66151SP
24-BIT I/O EXPANDER
REJ03F0258-0100
Rev. 1.00
Jan.08.2008
DESCRIPTION
R8A66151 is a semiconductor integrated circuit which has 24-bit shift register function to execute serial in -
parallel out conversion and parallel in - serial out conversion.
Built in two shift registers for serial in - parallel out and parallel in - serial out are constructed independently,
This IC is able to read serial input data into a shift register while output the serial data converting from the
parallel data input.
Also, parallel data I/O pins can be set to input mode or output mode by a bit.
R8A66151 is useful in a wide range of applications, such as MCU (micro controller unit) I/O port extension
and serial bus system data communication. R8A66151 is the succession product of M66010.
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FEATURES
Bi-directional serial communication with MCU
Serial data can be input during parallel to serial data conversion
Parallel data I/O pins can be set input mode or output mode by a bit
Schmitt input (DI, CLK, /S, /CS)
N-ch open drain output (DO, D1~D24)
Parallel data I/O pins (D1~D24)
Wide supply voltage range (Vcc=2.0 to 6.0V)
Wide operating temperature range (Ta=-40 to 85oC)
APPLICATION
Serial - parallel or parallel - serial data conversion for MCU peripheral.
Serial bus control by MCU.
PIN CONFIGURATION (TOP VIEW)
SERIAL DATA OUTPUT DO
SERIAL DATA INPUT DI
CLOCK INPUT CLK
CHIP SELECT INPUT CS
Vcc
SET INPUT S
GND
D24
D23
D22
D21
D20
D19
D18
D17
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 D1
31 D2
30 D3
29 D4
28 D5
27 D6
26 D7
25 D8
24 D9
PARALLEL DATA
I/O
23 D10
22 D11
21 D12
20 D13
19 D14
18 D15
17 D16
REJ03F0258-0100 Rev.1.00 Jan.08.2008
Page 1 of 7
1 page  
R8A66151SP
SWITCHING CHARACTERISTICS
Symbol
Parameter
fmax
tPLZ
tPZL
tPLZ
tPZL
tPLZ
Maximum repeat frequency
Output "L-Z" and "Z-L" propagation time
CLK - DO
Output "L-Z" and "Z-L" propagation time
/CS - D1~D24
Output "L-Z" propagation time
/S - DO, /S - D1~D24
(Vcc=2.0~6.0V, Ta=-40~85oC, unless otherwise noted)
Test conditions Min.
CL=50pF
RL=1kΩ
(note1)
Limits
Typ.
Max.
1.9
400
400
400
400
400
Unit
MHz
ns
ns
ns
ns
ns
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TIMING REQUIREMENTS (Vcc=2.0~6.0V, Ta=-40~85oC, unless otherwise noted)
Symbol
Parameter
tw CLK, /CS, /S pulse width
Setup time of DI to CLK
tsu Setup time of /CS to CLK
Setup time of D1~D24 to /CS
Hold time of DI to CLK
th Hold time of /CS to CLK
Hold time of D1~D24 to /CS
trec Recovery time of /CS to /S
Test conditions
Min.
260
130
130
130
130
130
130
130
Limits
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTE1: TEST CIRCUIT
Input
Vcc
P.G.
50 Ω
DUT
GND
Vcc
RL
CL
DO,
D1~D24
(1) The pulse generator (P.G.) has the following characteristics
(10%~90%) tr=6ns, tf=6ns, Zo=50 Ω
(2) The capacitance CL includes stray wiring capacitance
and the probe input capacitance.
REJ03F0258-0100 Rev.1.00 Jan.08.2008
Page 5 of 7
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet R8A66151SP.PDF ] | |
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